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C9851 の電気的特性と機能

C9851のメーカーはCypress Semiconductorです、この部品の機能は「Clock Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 C9851
部品説明 Clock Generator
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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C9851 Datasheet, C9851 PDF,ピン配置, 機能
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PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Product Features
Six pairs of current referenced differential clocks
Two 3V 180° displaced Mref clocks for DRCG
One 66.6 MHz reference output
One 14.318 MHz reference output
Select logic for Differential Swing Control, Test
mode, Hi-Z, Power-down, Spread spectrum, and
limited frequency select
Cypress Spread Spectrum for EMI reduction
48 Pin SSOP Package
Frequency Selection Table
SEL 100/133 SELA SELB CPU(1:6), CPU#(1:6)
0 00
100 MHz
0 01
100 MHz
0 10
200 MHz
0 11
Hi-Z
1 0 0 133.3 MHz
1 01
25 MHz
1 10
200 MHz
1 11
REF/2
Block Diagram
Product Description
This device provides the necessary clocks for a
differential host bus system in multi-processor servers
and workstations. It also generates a 66.6MHz hub
clock for interfacing with a complimentary part, the
Cypress B9852. The 2 Mref clock outputs are 180
degrees out of phase and are used for interfacing with
the Direct Rambus Clock Generator (DRCG), C9820,
C9821, or C9822. This device integrates the Cypress
spread spectrum technology for optimum EMI
reduction.
3VMref,
3Vmref_b
50 MHz
Low
50 MHz
Hi-Z
66.67 MHz
50 MHz
66.7 MHz
REF/4
Table 1
3V66
66.67 MHz
Low
66.67 MHz
Hi-Z
66.67 MHz
66.67 MHz
66.67 MHz
REF
Pin Configuration
REF
14.318 MHz
Low
14.318 MHz
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
REF
XIN OSC
XOUT
MultSel(0:1)
Spread#
SelA
SelB
SEL100/133
VCO
PwrDwn#
I
Control
VDDR
REF
VSSR
VDDA
I_Ref
VSSI
CPU (1:6)
CPU (1:6)#
VDDM
3VMRef
3VMRef_b
VSSM
VDDL
3V66
VSSL
VSSR
Ref
VDDR
XIN
XOUT
VSSR
VDDM
3VMref
3VMref_b
VSSM
VDD
VSS
VDDL
3V66
VSSL
SEL100/133
MultSel0
MultSel1
VDDA
VSSA
SelA
SelB
Spread#
PwrDwn#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDD
47 VSS
46 VDDC
45 CPU1
44 CPU1#
43 VSSC
42 CPU2
41 CPU2#
40 VDDC
39 CPU3
38 CPU3#
37 VSSC
36 CPU4
35 CPU4#
34 VDDC
33 CPU5
32 CPU5#
31 VSSC
30 CPU6
29 CPU6#
28 VDDC
27 I_Ref
26 VSSA
25 VDDA
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 1 of 14

1 Page





C9851 pdf, ピン配列
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS - 0.5V
Maximum Input Voltage Relative to VSS: VDD + 0.7V
Storage Temperature:
-65ºC to + 150ºC
Operating Temperature:
0ºC to +70ºC
Maximum ESD protection
2000V
Maximum Power Supply:
5.5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters (VDDI = VDD = VDDR = VDDL = VDDM = VDDC = 3.3V ±5%, TA = 0°C to +70°C)
Characteristic
Symbol Min
Typ Max
Units
Conditions
Input Low Voltage
Input High Voltage
VIL1
-
- 0.8 Vdc
VIH1
2.0
-
- Vdc
Note 1
Input Low Current (@Vin =
VSS)
Input High Current (@Vin =
VDD)
IIL
IIH
-16
0
-4 µA For internal Pull up resistors, Note 1
and Note 2
5 µA
-
Input Low Current (@Vin =
VSS)
IIL
0
- µA For internal Pull down resistors, Note
1 and Note 2
Input High Current (@Vin =
VDD)
IIH
4
16 µA
Tri-State leakage Current
Ioz
-
- 10 µA
Static Supply Current
Idd - - 30 mA
PwrDwn=Low
Dynamic Supply Current Isdd -
- 200 mA
133 MHz CPU, Note 3
Input pin capacitance
Cin - - 5 pF
Output pin capacitance
Cout
-
-
6 pF
Pin Inductance
Lpin - - 7 nH
Crystal pin capacitance
Cxtal 34 36 38 pF Measured from Pin to Ground. See
crystal specification section presented
later in this data sheet.
Crystal Startup time
Txs -
- 40 µS From Stable 3.3V power supply.
Internal Pull-up and Pull-
down resistor value
Rpi 200 250 500 K
Note1: Applicable to input signals: Sel100/133, Sel(A:B)), Spread#, PWRDN#, MultSel(0:1)
Note2: Although internal pull-up or Pull-Down resistors have a typical value of 250K, this value may vary between 200K and 500K.
Note3: All outputs loaded as per the maximum capacitive table in this data sheet.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 3 of 14


3Pages


C9851 電子部品, 半導体
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Lumped Test Load Configurations (Cont.)
Output under Test
Probe
Load Cap
-
2.4V
1.5V
0.4V
Tr
3.3V signals
tDC
3.3V
0V
Tf
-
Fig. 1B
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic
Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the
center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore
spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from
(Fig.2) its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). The
default of the device at power up keeps the Spread Spectrum disabled, therefore, in order to enable this function pin23,
Spread#, must be connect to ground (a low state.). See table 3 for Spread bandwidth description.
In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by -0.25%. (ex.:
assuming the center frequency is 100MHz in non-spread mode; when down spread is enabled, the center frequency
shifts to 99.75MHz.).
In Center Spread mode, the Center frequency remains the same as in the non-spread mode.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 6 of 14

6 Page



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部品番号部品説明メーカ
C9851

Clock Generator

Cypress Semiconductor
Cypress Semiconductor


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