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3D3523 の電気的特性と機能

3D3523のメーカーはData Delay Devicesです、この部品の機能は「MONOLITHIC MANCHESTER ENCODER/DECODER」です。


製品の詳細 ( Datasheet PDF )

部品番号 3D3523
部品説明 MONOLITHIC MANCHESTER ENCODER/DECODER
メーカ Data Delay Devices
ロゴ Data Delay Devices ロゴ 




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3D3523 Datasheet, 3D3523 PDF,ピン配置, 機能
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MONOLITHIC MANCHESTER
ENCODER/DECODER
(SERIES 3D3523)
FEATURES
All-silicon, low-power CMOS technology
Encoder and decoder function independently
Encoder has buffered clock output
3.3V operation
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Maximum data rate: 50 MBaud
Data rate range: ±15%
Lock-in time: 1 bit
For mechanical dimensions, click here.
For package marking details, click here.
3D3523
ddealtaay 3
devices, inc.
PACKAGES
CIN 1 14 VDD
CEN 2 13 CBUF
RX 3 12 LOOP
COUT 4 11 TXENB
DIN 5 10 DOUTB
RESB 6
9 TXB
GND 7
8 TX
3D3523-xxx DIP (.300)
3D3523G-xxx Gull Wing (.300)
3D3523D-xxx SOIC (.150)
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3523 is a monolithic CMOS Manchester Encoder/Decoder combo
chip. The device uses bi-phase-level encoding to embed a clock signal
into a data stream for transmission across a communications link. In this
encoding mode, a logic one is represented by a high-to-low transition in
the center of the bit cell, while a logic zero is represented by a low-to-high
transition.
The Manchester encoder combines the clock (CIN) and data (DIN) into a
single bi-phase-level signal (TX). An inverted version of this signal (TXB) is
also available. The data baud rate (in MBaud) is equal to the input clock
frequency (in MHz). A replica of the clock input is also available (CBUF).
The encoder may be reset by setting the RESB input low; otherwise, it
should be left high. The TX and TXB signals may be disabled (high-Z) by
setting TXENB high. Similarly, CBUF may be disabled by setting CEN low.
Under most operating conditions, TX and TXB are always enabled, and
CBUF is not used. With this in mind, the 3D3523 provides internal pull-
down resistors on CEN and TXENB, so that most users can leave these
inputs uncommitted.
Encoder:
CIN Clock Input
DIN Data Input
RESB Reset
CEN Clock buffer enable
TXENB Transmit enable
CBUF Buffered clock
TX,TXB Transmitted signal
Decoder:
RX Received Signal
COUT Recovered Clock
DOUTB Recovered Data
Common:
LOOP Loop enable
VDD +3.3 Volts
GND Ground
The Manchester decoder accepts the embedded-clock signal at the RX input. The recovered clock and
data signals are presented on COUT and DOUTB, respectively, with the data signal inverted. The
operating baud rate (in MBaud) is specified by the dash number of the device. The input baud rate may
vary by as much as ±15% from the nominal device baud rate without compromising the integrity of the
information received.
Because the decoder is not PLL-based, it does not require a long preamble in order to lock onto the
received signal. Rather, the device requires at most one bit cell before the data presented at the output is
valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise
turned off.
Normally, the encoder and decoder function independently. However, if the LOOP input is set high, the
encoded TX signal is fed back internally into the decoder and the RX input is ignored. This feature is
useful for diagnostics. The LOOP input has an internal pull-down resistor and may be left uncommitted if
this feature is not needed.
2006 Data Delay Devices
Doc #06006
5/8/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1

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3D3523 pdf, ピン配列
3D3523
APPLICATION NOTES (CONT’D)
DECODER
The Manchester decoder subsystem samples the
input at precise pre-selected intervals to retrieve
the data and to recover the clock from the
received data stream. Its architecture comprises
finely tuned delay elements and proprietary
circuitry which, in conjunction with other circuits,
implement the data decoding and clock recovery
function.
Typically, the encoded data transmitted from a
source arrives at the decoder corrupted. Such
corruption of the received data manifests itself as
jitter and/or pulse width distortion at the decoder
input. The instantaneous deviations from
nominal Baud Rate and/or Pulse Width (high or
low) adversely impact the data extraction and
clock recovery function if their published limits
are exceeded. See Table 4, Allowed Baud
Rate/Duty Cycle. The decoder, being a self-
timed device, is tolerant of frequency modulation
(jitter) present in the input data stream, provided
that the input data pulse width variations remain
within the allowable ranges.
The decoder presents at its outputs the decoded
data (inverted) and the recovered clock. The
decoded data is valid at the rising edge of the
clock.
The clock recovery function operates in two
modes dictated by the input data stream bit
sequence. When a data bit is succeeded by its
inverse, the clock recovery circuit is engaged and
forces the clock output low for a time equal
to one over twice the baud rate. Otherwise, the
input is presented at the clock output unchanged,
shifted in time. Therefore, the clock duty cycle is
strongly dependent on the baud rate, as this will
affect the clock-high duration.
The clock output falling edge is not operated on
by the clock recovery circuitry. It, therefore,
preserves more accurately the clock frequency
information embedded in the transmitted data. It
can therefore be used, if desired, to retrieve clock
frequency information.
INPUT SIGNAL CHARACTERISTICS
The 3D3523 inputs are CMOS compatible. The
user should assure him/herself that the 50%
(of VDD) threshold is used when referring to all
timing, especially to the input clock duty cycle
(encoder) and the received data (decoder).
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry is strongly dependent
on power supply and temperature. The
monolithic 3D3523 Manchester encoder/decoder
utilizes novel and innovative compensation
circuitry to minimize timing variations induced by
fluctuations in power supply and/or temperature.
Nevertheless, optimum performance is achieved
by providing a stable power supply and a clean
ground plane, and by placing a bypass capacitor
(0.1uf typically) as close to the device as
possible.
ENCODED
RECEIVED
(RX)
0
CLOCK
(CLK)
DATA
(DATB)
DECODED
Doc #06006
5/8/2006
1011001
tC
tCL tCWL
tCD
10110
Figure 2: Timing Diagram (Decoder)
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
0
1
3


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共有リンク

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