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PDF IS62LV12816BLL Data sheet ( Hoja de datos )
| Número de pieza | IS62LV12816BLL | |
| Descripción | ULTRA LOW POWER CMOS STATIC RAM | |
| Fabricantes | ISSI | |
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IS62LV12816BLL
128K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
ISSI®
FEBRUARY 2001
FEATURES
• High-speed access time: 55, 70, 100 ns
• CMOS low power operation
– 120 mW (typical) operating
– 6 µW (typical) CMOS standby
• TTL compatible interface levels
• Single 2.7V-3.45V VCC power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (6mm x 8mm)
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS62LV12816BLL is a high-speed, 2,097,152-bit
static RAM organized as 131,072 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
When CE is HIGH (deselected) or when CE is low and
both LB and UB are HIGH, the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62LV12816BLL is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA (6mm x 8mm).
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
03/07/01
1
1 page  
IS62LV12816BLL
ISSI ®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
ICC Vcc Dynamic Operating
Supply Current
ISB1 TTL Standby Current
(TTL Inputs)
OR
Test Conditions
VCC = Max.,
IOUT = 0 mA, f = fMAX
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH , f = 0
Com.
Ind.
Com.
Ind.
-55
Min. Max.
— 40
— 45
— 0.4
— 1.0
ULB Control
VCC = Max., VIN = VIH or VIL
CE = VIL, f = 0, UB = VIH, LB = VIH
-70
Min. Max.
— 30
— 35
— 0.4
— 1.0
-100
Min. Max.
— 20
— 25
— 0.4
— 1.0
Unit
mA
mA
ISB2 CMOS Standby
VCC = Max.,
Com.
Current (CMOS Inputs) CE ≥ VCC – 0.2V,
Ind.
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
OR
—5
—5
—5
—5
—5
—5
µA
ULB Control
VCC = Max., CE = VIL
VIN ≤ 0.2V, f = 0; UB / LB = VCC – 0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
1
2
3
4
5
6
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
-55
Min. Max.
-70
Min. Max.
-100
Min. Max.
Unit
tRC Read Cycle Time
55 —
70 —
100 —
ns
tAA Address Access Time — 55
— 70
— 100
ns
tOHA Output Hold Time
10 —
10 —
15 —
ns
tACE CE Access Time
— 55
— 70
— 100
ns
tDOE OE Access Time
— 30
— 35
— 50
ns
tHZOE(2) OE to High-Z Output
— 20
— 25
— 30
ns
tLZOE(2) OE to Low-Z Output
5—
5—
5—
ns
tHZCE(2) CE to High-Z Output
0 20
0 25
0 30
ns
tLZCE(2) CE to Low-Z Output
10 —
10 —
10 —
ns
tBA
LB, UB Access Time
— 55
— 70
— 100
ns
tHZB
LB, UB to High-Z Output 0
25
0 25
0 35
ns
tLZB
LB, UB to Low-Z Output 0
—
0—
0—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of
0.4 to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
03/07/01
5
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