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ADM1067 の電気的特性と機能

ADM1067のメーカーはAnalog Devicesです、この部品の機能は「Super Sequencer」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADM1067
部品説明 Super Sequencer
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADM1067 Datasheet, ADM1067 PDF,ピン配置, 機能
Data Sheet
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP4 (VPx)
5 dual-function inputs, VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs, PDO1 to PDO10 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Open-loop margining solution for 6 voltage rails
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead, 6 mm × 6 mm LFCSP and
48-lead, 7 mm × 7 mm TQFP packages
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
Super Sequencer with
Open-Loop Margining DACs
ADM1067
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND SDA SCL A1 A0
ADM1067
VREF
SMBus
INTERFACE
EEPROM
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
VDDCA P
MUP
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
GND
VCCP
MDN
DAC1
DAC2
DAC3
DAC4
Figure 1.
DAC5
DAC6
GENERAL DESCRIPTION
The ADM1067 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems. In addition
to these functions, the ADM1067 integrates six 8-bit voltage
output DACs. These circuits can be used to implement an open-
loop margining system that enables supply adjustment by altering
either the feedback node or reference of a dc-to-dc converter
using the DAC outputs.
For more information about the ADM1067 register map, refer
to the AN-698 Application Note.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page





ADM1067 pdf, ピン配列
ADM1067
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Detailed Block Diagram .................................................................. 4
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Powering the ADM1067 ................................................................ 14
Slew Rate Consideration............................................................ 14
Inputs................................................................................................ 15
Supply Supervision..................................................................... 15
Programming the Supply Fault Detectors............................... 15
Input Comparator Hysteresis.................................................... 15
Input Glitch Filtering ................................................................. 16
Supply Supervision with VXx Inputs....................................... 16
VXx Pins as Digital Inputs ........................................................ 16
Outputs ............................................................................................ 17
Supply Sequencing Through Configurable Output Drivers.......17
Default Output Configuration.................................................. 17
Sequencing Engine ......................................................................... 18
Data Sheet
Overview ..................................................................................... 18
Warnings...................................................................................... 18
SMBus Jump (Unconditional Jump)........................................ 18
Sequencing Engine Application Example ............................... 19
Fault and Status Reporting........................................................ 20
Supply Margining ........................................................................... 21
Overview ..................................................................................... 21
Open-Loop Supply Margining ................................................. 21
Writing to the DACs .................................................................. 21
Choosing the Size of the Attenuation Resistor....................... 22
DAC Limiting and Other Safety Features ............................... 22
Applications Diagram .................................................................... 23
Communicating with the ADM1067........................................... 24
Configuration Download at Power-Up................................... 24
Updating the Configuration ..................................................... 24
Updating the Sequencing Engine............................................. 25
Internal Registers........................................................................ 25
EEPROM ..................................................................................... 25
Serial Bus Interface..................................................................... 25
SMBus Protocols for RAM and EEPROM.............................. 28
Write Operations ........................................................................ 28
Read Operations......................................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
Rev. E | Page 2 of 31


3Pages


ADM1067 電子部品, 半導体
Data Sheet
ADM1067
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPx
VPx
VH
VDDCAP
CVDDCAP
POWER SUPPLY
Supply Current, IVH, IVPx
Additional Currents
All PDO FET Drivers On
Current Available from VDDCAP
DACs Supply Current
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPx Pins
Input Impedance
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VXx Pins
Input Impedance
Detection Ranges
Ultralow Range
Absolute Accuracy
Threshold Resolution
Digital Glitch Filter
BUFFERED VOLTAGE OUTPUT DACs
Resolution
Code 0x80 Output Voltage
Range 1
Range 2
Range 3
Range 4
Output Voltage Range
LSB Step Size
Min Typ
3.0
2.7 4.75
10
4.2
1
2.2
1
10
Max Unit Test Conditions/Comments
V
6.0 V
14.4 V
5.4 V
μF
Minimum supply required on one of VH, VPx
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
6 mA VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off
mA VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO10 off
2 mA Maximum additional load that can be drawn from all PDO
pull-ups to VDDCAP
mA Six DACs on with 100 μA maximum load on each
mA Running round-robin loop
mA 1 ms duration only, VDDCAP = 3 V
52
±0.05
% Midrange and high range
6 14.4 V
2.5 6 V
52
±0.05
% Low range and midrange
2.5
1.25
0.573
6
3
1.375
V
V
V
No input attenuation error
1 MΩ
0.573
8
0
100
1.375 V
±1 %
Bits
μs
μs
No input attenuation error
VREF error + DAC nonlinearity + comparator offset error +
input attenuation error
Minimum programmable filter length
Maximum programmable filter length
8 Bits
0.592
0.796
0.997
1.247
0.6
0.8
1
1.25
601.25
2.36
0.603
0.803
1.003
1.253
V
V
V
V
mV
mV
Six DACs are individually selectable for centering on one of
four output voltage ranges
Same range, independent of center point
Rev. E | Page 5 of 31

6 Page



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