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PDF AD9640 Data sheet ( Hoja de datos )
| Número de pieza | AD9640 | |
| Descripción | Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
SNR = 71.8 dBc (72.8 dBFS) to 70 MHz @ 125 MSPS
SFDR = 85 dBc to 70 MHz @ 125 MSPS
Low power: 750 mW @ 125 MSPS
SNR = 71.6 dBc (72.6 dBFS) to 70 MHz @ 150 MSPS
SFDR = 84 dBc to 70 MHz @ 150 MSPS
Low power: 820 mW @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3V CMOS output supply or 1.8 V LVDS
output supply
Integer 1 to 8 input clock divider
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, WCDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
14-Bit, 80/105/125/150 MSPS, 1.8 V
Dual Analog-to-Digital Converter
AD9640
FUNCTIONAL BLOCK DIAGRAM
SDIO/ SCLK/
AVDD DVDD FD(0:3)A DCS DFS CSB DRVDD
FD BITS/THRESHOLD
DETECT
SPI
VIN+A
VIN–A
VREF
SENSE
CML
RBIAS
VIN–B
VIN+B
SHA
REF
SELECT
ADC
PROGRAMMING DATA
SIGNAL
MONITOR
DIVIDE
1 TO 8
DUTY CYCLE
STABILIZER
DCO
GENERATION
SHA
ADC
SIGNAL MONITOR
DATA
MULTICHIP FD BITS/THRESHOLD SIGNAL MONITOR
SYNC
DETECT
INTERFACE
D13A
D0A
CLK+
CLK–
DCOA
DCOB
D13B
D0B
AGND SYNC
FD(0:3)B
Figure 1.
SMI SMI SMI DRGND
SDFS SCLK/ SDO/
PDWN OEB
PRODUCT HIGHLIGHTS
1. Integrated dual 14-bit, 80/105/125/150 MSPS ADC.
2. Fast overrange detect and signal monitor with serial output.
3. Signal monitor block with dedicated serial output mode.
4. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 450 MHz.
5. Operation from a single 1.8 V supply and a separate digital
output driver supply to accommodate 1.8 V to 3.3 V logic
families.
6. A standard serial port interface that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, and voltage reference mode.
7. Pin compatibility with the AD9627, AD9627-11, and the
AD9600 for a simple migration from 14 bits to 12 bits, 11
bits, or 10 bits.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
1 page  
AD9640
GENERAL DESCRIPTION
The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-to-
digital converter (ADC). The AD9640 is designed to support
communications applications where low cost, small size, and
versatility are desired.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth differential sample-and-hold
analog input amplifiers supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to compen-
sate for variations in the ADC clock duty cycle, allowing the
converters to maintain excellent performance.
The AD9640 has several functions that simplify the automatic
gain control (AGC) function in the system receiver. The fast detect
feature allows fast overrange detection by outputting four bits of
input level information with very short latency.
In addition, the programmable threshold detector allows moni-
toring of the incoming signal power using the four fast detect
bits of the ADC with very low latency. If the input signal level
exceeds the programmable threshold, the fine upper threshold
indicator goes high. Because this threshold is set from the four
MSBs, the user can quickly turn down the system gain to avoid an
overrange condition.
The second AGC-related function is the signal monitor. This
block allows the user to monitor the composite magnitude of
the incoming signal, which aids in setting the gain to optimize
the dynamic range of the overall system.
The ADC output data can be routed directly to the two external
14-bit output ports. These outputs can be set from 1.8 V to 3.3 V
CMOS or 1.8 V LVDS.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a
3-bit SPI-compatible serial interface.
The AD9640 is available in a 64-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C.
Rev. B | Page 4 of 52
5 Page 
AD9640
Parameter
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 3.3 V
High Level Output Voltage (IOH = 50 μA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 μA)
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage (IOH = 50 μA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 μA)
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS), Reduced Swing Mode
1 Pull up.
2 Pull down.
Temperature Min
Full 3.29
Full 3.25
Full
Full
Full 1.79
Full 1.75
Full
Full
Full 250
Full 1.15
Full 150
Full 1.15
Typ Max
0.2
0.05
0.2
0.05
350 450
1.25 1.35
200 280
1.25 1.35
Unit
V
V
V
V
V
V
V
V
mV
V
mV
V
SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND
AD9640BCPZ-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 6.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate
DCS Enabled1
DCS Disabled1
CLK Period—Divide by 1 Mode (tCLK)
CLK Pulse Width High
Divide by 1 Mode, DCS Enabled
Divide by 1 Mode, DCS Disabled
Divide by 2 Mode, DCS Enabled
Divide by 3 Through 8, DCS Enabled
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9640ABCPZ-80
AD9640BCPZ-80
Min Typ
Max
625
20 80
10 80
12.5
3.75 6.25
5.63 6.25
1.6
0.8
8.75
6.88
AD9640ABCPZ-105/
AD9640BCPZ-105
Min Typ
Max
625
20 105
10 105
9.5
2.85 4.75
4.28 4.75
1.6
0.8
6.65
5.23
Unit
MHz
MSPS
MSPS
ns
ns
ns
ns
ns
2.2 4.5
3.8 5.0
6.25
5.75
2.4 5.2
4.0 5.6
3.0 3.7
5.4 7.0
6.4 2.2 4.5
6.8 3.8 5.0
5.25
4.25
6.9 2.4 5.2
7.3 4.0 5.6
4.4 3.0 3.7
8.4 5.2 6.4
6.4 ns
6.8 ns
ns
ns
6.9 ns
7.3 ns
4.4 ns
7.6 ns
Rev. B | Page 10 of 52
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9640.PDF ] | |
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