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PDF ADN2807 Data sheet ( Hoja de datos )
| Número de pieza | ADN2807 | |
| Descripción | Clock and Data Recovery IC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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155/622 Mb/s Clock and Data Recovery IC
with Integrated Limiting Amp
ADN2807
FEATURES
Meets SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: ±100 mV
Patented clock recovery architecture
Loss-of-signal detect range: 3 mV to 15 mV
Single-reference clock frequency for all rates, including
15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or
155.52 MHz REFCLK
REFCLK inputs: LVPECL/LVDS/LVCMOS/LVTTL compatible
(LVPECL/LVDS only at 155.52 MHz)
Optional 19.44 MHz on-chip oscillator to be used with
external crystal
Loss-of-lock indicator
Loopback mode for high speed test data
Output squelch and bypass features
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm × 7 mm, 48-lead LFCSP
GENERAL DESCRIPTION
The ADN2807 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at rates of OC-3,
OC-12, and 15/14 FEC. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance. All
specifications are quoted for –40°C to +85°C ambient
temperature, unless otherwise noted.
The device is intended for WDM system applications and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both native rates and 15/14 rate
digital wrappers are supported by the ADN2807, without any
change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at the
output.
APPLICATIONS
SONET OC-3/-12, SDH STM-1/-4 and, 15/14 FEC rates
WDM transponders
The ADN2807 is available in a compact 7 mm × 7 mm 48-lead
chip-scale package (LFCSP).
Regenerators/repeaters
Test equipment
Passive optical networks
FUNCTIONAL BLOCK DIAGRAM
SLICEP/N
VCC VEE
CF1 CF2
LOL
2 ADN2807
PIN
QUANTIZER
NIN
PHASE
SHIFTER
PHASE
DET.
LOOP
FILTER
LOOP
FILTER
VCO
FREQUENCY
LOCK
DETECTOR
VREF
LEVEL
DETECT
THRADJ SDOUT
DATA
RETIMING
2
DATAOUTP/N
DIVIDER
1/2/4/16
2
CLKOUTP/N
FRACTIONAL
DIVIDER
3
SEL[0..2]
2
2
/n
XTAL
OSC
REFSEL[0..1]
REFCLKP/N
XO1
XO2
REFSEL
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltage (VCC)
5.5 V
Minimum Input Voltage (All Inputs) VEE – 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature
165°C
Storage Temperature
–65°C to +150°C
Lead Temperature (Soldering 10 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ADN2807
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LFCSP, 4-layer board with exposed paddle soldered
to VCC
θJA = 25°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 20
5 Page 
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At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track the input jitter. In this case,
the VCO control voltage becomes large and saturates, and the
VCO frequency dwells at one or the other extreme of its tuning
range. The size of the VCO tuning range, therefore, has only a
small affect on the jitter accommodation. The delay-locked loop
control voltage is now larger; therefore, the phase shifter takes
on the burden of tracking the input jitter. The phase shifter
range, in UI, can be seen as a broad plateau on the jitter
tolerance curve. The phase shifter has a minimum range of 2 UI
at all data rates.
The gain of the loop integrator is small for high jitter
frequencies, so larger phase differences are needed to make the
loop control voltage big enough to tune the range of the phase
shifter. Large phase errors at high jitter frequencies cannot be
tolerated. In this region, the gain of the integrator determines
the jitter accommodation. Since the gain of the loop integrator
declines linearly with frequency, jitter accommodation is lower
with higher jitter frequency. At the highest frequencies, the loop
gain is very small, and little tuning of the phase shifter can be
expected. In this case, jitter accommodation is determined by
ADN2807
the eye opening of the input data, the static phase error, and the
residual loop jitter generation. The jitter accommodation is
roughly 0.5 UI in this region. The corner frequency between the
declining slope and the flat region is the closed loop bandwidth
of the delay-locked loop, which is roughly 5 MHz for OC-12
data rates and 600 kHz for OC-3 data rates.
JITTER PEAKING
IN ORDINARY PLL
JITTER
GAIN
(dB)
ADN2807
Z(s)
X(s)
o
n psh
d psh
c
f (kHz)
Figure 14. Jitter Response vs. Conventional PLL
Rev. A | Page 11 of 20
11 Page | ||
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