PDF IS25C256 Data sheet ( Hoja de datos )

Número de pieza	IS25C256
Descripción	(IS25C128 / IS25C256) 128K-bit/ 256K-bit SPI SERIAL ELECTRICALLY ERASABLE PROM
Fabricantes	ISSI
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No Preview Available ! www.DataSheet4U.com IS25C128 IS25C256 128K-bit/ 256K-bit SPI SERIAL ELECTRICALLY ERASABLE PROM ISSI® Advanced Information JULY 2006 FEATURES • Serial Peripheral Interface (SPI) Compatible — Supports SPI Modes 0 (0,0) and 3 (1,1) • Low power CMOS — Active current less than 3.0 mA (2.5V) — Standby current less than 20 µA (2.5V) • Low-voltage Operation — Vcc = 1.8V to 5.5V • Block Write Protection — Protect 1/4, 1/2, or Entire Array • 64 byte page write mode — Partial page writes allowed • 2.1 MHz Clock Rate (5V) • Self timed write cycles — 5ms max @ 2.5V • High-reliability — Endurance: 1,000,000 cycles per byte — Data retention: 100 years • 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin PDIP packages available • Industrial and Automotive temperature ranges • Lead-free available DESCRIPTION The IS25C128 and IS25C256 are electrically erasable PROM devices that use the Serial Peripheral Interface (SPI) for communications. The IS25C128 is 128Kbit (16K x 8) and the IS25C256 is 256Kbit (32K x 8). The IS25C128/256 EEPROMs are offered in a wide operating voltage range of 1.8V to 5.5V for compatibility with most application voltages. ISSI designed the IS25C128/256 to be an efficient SPI EEPROM solution. The devices are packaged in 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin PDIP. The functional features of the IS25C128/256 allow them to be among the most advanced serial non-volatile memories available. Each device has a Chip-Select (CS) pin, and a 3-wire interface of Serial Data In (SI), Serial Data Out (SO), and Serial Clock (SCK). While the 3-wire interface of the IS25C128/256 provides for high-speed access, a HOLD pin allows the memories to ignore the interface in a suspended state; later the HOLD pin re-activates communication without re- initializing the serial sequence. A Status Register facilitates a flexible write protection mechanism, and a device-ready bit (RDY). Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Advanced Information Rev. 00E 06/13/06 1 1 page IS25C128 IS25C256 ISSI ® DEVICE OPERATION The operations of the IS25C128/256 are controlled by a set of instructions that are clocked-in serially SI pin. (See Table 3). To begin an instruction, the chip select (CS) should be dropped Low. Subsequently, each Low-to-High transition of the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to continue to input an address or data to SI, or to output data from SO. During data output, values appear on the falling edge of SK. All bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Low- to-High transition of SK, CS should be raised High to end the transaction. The device then would enter Standby Mode if no internal programming were underway. Table 3. Instruction Set Name Op-code Operation Address Data(SI) Data (SO) WREN 0000 X110 Set Write Enable Latch - -- WRDI RDSR WRSR READ WRITE 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010 Reset Write Enable Latch Read Status Register Write Status Register Read Data from Array Write Data to Array - - - A15-A0 A15-A0 - - D7-D0 - D7-D0,... - D7-D0,... - D7-D0,... - Notes: 1. X = Don’t care bit. For consistency, it is best to use “0”. 2. Some address bits are don’t care. See Table 5. 3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no affect. A valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the array or Status Register to be ignored. WRITE ENABLE (WREN) When Vcc is initially applied, the device powers up with both status register and entire array in a write-disabled state. Upon completion of Write Disable (WRDI), Write Status Register (WRSR), or Write Data to Array (WRITE), the device resets the WEN bit in the Status Register to 0. Prior to any data modification, a WREN instruction is necessary to set WEN to 1. (See Figure 2 for timing). WRITE DISABLE (WRDI) The device can be completely protected from modifica- tion by resetting WEN to 0 through the WRDI instruc- tion. (See Figure 3 for timing). READ STATUS REGISTER (RDSR) The Read Status instruction tells the user the status of Write Protect Enable, the Block Protection setting (see Table 2), the Write Enable state, and the RDY status. RDSR is the only instruction accepted when a write cycle is underway. It is recommended that the status of Write Enable and RDY be checked, especially prior to an attempted modification of data. The 8 bits of the Status Register can be repeatedly output on SO after the initial Op-code. (See Figure 4 for timing). Integrated Silicon Solution, Inc. — 1-800-379-4774 AdvancedInformation Rev. 00E 06/13/06 5 5 Page IS25C128 IS25C256 TIMING DIAGRAMS Figure 1. Synchronous Data Timing VIH CS VIL VIH SK VIL VIH DIN VIL tCSS tWH tSU tH VALID IN DOUT VOH VOL HIGH-Z tWL tV Figure 2. WREN Timing CS SK DIN DOUT Figure 3. WRDI Timing CS SK DIN DOUT WREN OP-CODE HIGH-Z WRDI OP-CODE HIGH-Z Integrated Silicon Solution, Inc. — 1-800-379-4774 AdvancedInformation Rev. 00E 06/13/06 ISSI ® tCS tCSH tHO tDIS HIGH-Z 11 11 Page

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