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IS25C08 の電気的特性と機能

IS25C08のメーカーはISSIです、この部品の機能は「(IS25C08 / IS25C16) 8K-BIT/16K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS25C08
部品説明 (IS25C08 / IS25C16) 8K-BIT/16K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS25C08 Datasheet, IS25C08 PDF,ピン配置, 機能
www.DataSheet4U.com
IS25C08
IS25C16
8K-BIT/16K-BIT SPI SERIAL
ELECTRICALLY ERASABLE PROM
ISSI®
Preliminary Information
APRIL 2006
FEATURES
• Serial Peripheral Interface (SPI) Compatible
— Supports SPI Modes 0 (0,0) and 3 (1,1)
• Wide-voltage Operation
— Vcc = 1.8V to 5.5V
• Low power CMOS
— Active current less than 3.0 mA (2.5V)
— Standby current less than 2.0 µA (2.5V)
• Block Write Protection
— Protect 1/4, 1/2, or Entire Array
• 16 byte page write mode
— Partial page writes allowed
• 10 MHz Clock Rate (5V)
• Self timed write cycles (5 ms Typical)
• High-reliability
— Endurance: 1 million cycles per byte
— Data retention: 100 years
• Industrial and Automotive temperature ranges
• 8-pin PDIP, 8-pin SOIC, 8-pin TSSOP, and chip scale
packages are available
• Lead-free available
DESCRIPTION
The IS25C08 and IS25C16 are electrically erasable
PROM devices that use the Serial Peripheral Interface
(SPI) for communications. The IS25C08 is 8Kbit
(1024x 8) and the IS25C16 is 16Kbit (2048 x 8). The
IS25C08/16 EEPROMs are offered in a wide operating
voltage range of 1.8V to 5.5V compatible with most
application voltages. ISSI designed the IS25C08/16 to
be an efficient SPI EEPROM solution. The devices are
packaged in 8-pin PDIP, 8-pin SOIC, 8-pin TSSOP, and
8-ball CSP.
The functional features of the IS25C08/16 allow them to
be among the most advanced serial non-volatile memo-
ries available. Each device has a Chip-Select (CS) pin,
and a 3-wire interface of Serial Data In (SI), Serial Data
Out (SO), and Serial Clock (SCK). While the 3-wire
interface of the IS25C08/16 provides for high-speed
access, a HOLD pin allows the memories to ignore the
interface in a suspended state; later the HOLD pin re-
activates communication without re-initializing the serial
sequence. A Status Register facilitates a flexible write
protection mechanism, and a device-ready bit (RDY).
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00H
02/23/06
1

1 Page





IS25C08 pdf, ピン配列
IS25C08
IS25C16
SERIAL INTERFACE DESCRIPTION
MASTER: The device that provides a clock signal.
SLAVE: The IS25C08/16 is a slave because the clock
signal is an input.
TRANSMITTER/RECEIVER: The IS25C08/16 has both
data input (SI) and data output (SO).
MSB: The most significant bit. It is always the first bit
transmitted or received.
OP-CODE: The first byte transmitted to the slave
following CS transition to LOW. If the OP-CODE is a
valid member of the IS25C08/16 instruction set (Table 3),
then it is decoded appropriately. If the OP-CODE is not
valid, and the SO pin remains in high impedance.
ISSI ®
BLOCK DIAGRAM
STATUS
REGISTER
VCC
GND
1024 x 8/2048 x 8
MEMORY ARRAY
DATA
REGISTER
SI
MODE
CS DECODE
LOGIC
WP
SCK
CLOCK
HOLD
Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00H
02/23/06
ADDRESS
DECODER
OUTPUT
BUFFER
SO
3


3Pages


IS25C08 電子部品, 半導体
IS25C08
IS25C16
ISSI ®
WRITE STATUS REGISTER (WRSR)
This instruction lets the user choose a Block Protection
setting, and set or reset the WPEN bit. The values of
the other data bits incorporated into WRSR can be 0 or
1, and are not stored in the Status Register. WRSR will
be ignored unless both the following are true: a) WEN =
1, due to a prior WREN instruction; and b) Hardware
Write Protection is not enabled. (See Table 4 for de-
tails). Except for the RDY status, the values in the
Status Register remain unchanged until the moment
when the write cycle is complete and the register is
updated. Note: WPEN can be changed from 1 to 0 only
if WP is already set High. Once completed, WEN is
reset for complete chip write protection. (See Figure 5 for
timing).
READ DATA (READ)
This instruction begins with the op-code and the 16-bit
address, and causes the selected data byte to be
shifted out on SO. Following this first data byte, addi-
tional sequential bytes are output. If the data byte in the
highest address is output, the address rolls-over to the
lowest address in the array, and the output could loop
indefinitely. At any time, a rising CS signal completes
the operation. (See Figure 6 for timing).
WRITE DATA (WRITE)
The WRITE instruction begins with the op-code, the 16-
bit address of the first byte to be modified, and the first
data byte. Additional data bytes may be written sequen-
tially to the array after the first byte. Each WRITE
instruction can affect the contents of a 16 byte page, but
no more. The page begins at address XXXXXXXX
XXXX0000, and ends with XXXXXXXX XXXX1111. If the last
byte of the page is input, the address rolls over to the
beginning of the same page. More than 16 data bytes
can be input during the same instruction, but upon a
completed write cycle, a page would only contain the
last 16 bytes.
The region of the array defined within Block Protection
cannot be modified as long as that block configuration is
selected. The region of the array outside the Block
Protection can only be modified if Write Enable (WEN) is
set to 1. Therefore, it may be necessary that a WREN
instruction occur prior to WRITE. Hardware Write
Protection has no affect on the memory array. Once
Write is completed, WEN is reset for complete chip
write protection. (See Figure 7 for timing).
Table 5. Address Key
Name
AN
Don't
Care Bits
IS25C08
A9-A0
A15-A10
IS25C16
A10-A0
A15-A11
Table 4. Write Protection
WPEN WP
Hardware Write
Protection
0 X Not Enabled
0 X Not Enabled
1 0 Enabled
1 0 Enabled
X 1 Not Enabled
X 1 Not Enabled
Note: X = Don't care bit.
WEN Inside Block Outside Block
0 Read-only
Read-only
1
Read-only
Unprotected
0 Read-only
Read-only
1
Read-only
Unprotected
0 Read-only
Read-only
1
Read-only
Unprotected
Status Register
(WPEN, BP1, BP0)
Read-only
Unprotected
Read-only
Read-only
Read-only
Unprotected
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00H
02/23/06

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
IS25C01

1K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

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IS25C02

(IS25C02 / IS25C04) 2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

ISSI
ISSI
IS25C04

(IS25C02 / IS25C04) 2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

ISSI
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IS25C08

(IS25C08 / IS25C16) 8K-BIT/16K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

ISSI
ISSI


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