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PDF IRFE320 Data sheet ( Hoja de datos )

Número de pieza IRFE320
Descripción REPETITIVE AVALANCHE AND dv/dt RATED HEXFET TRANSISTORS SURFACE MOUNT
Fabricantes International Rectifier 
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No Preview Available ! IRFE320 Hoja de datos, Descripción, Manual

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PD - 93985
REPETITIVE AVALANCHE AND dv/dt RATED
HEXFETTRANSISTORS
SURFACE MOUNT (LCC-18)
Product Summary
Part Number BVDSS
IRFE320
400V
RDS(on) ID
1.81.8A
IRFE320
JANTX2N6792U
JANTXV2N6792U
[REF:MIL-PRF-19500/555]
400V, N-CHANNEL
The leadless chip carrier (LCC) package represents the
logical next step in the continual evolution of surface
mount technology. Desinged to be a close replacement
for the TO-39 package, the LCC will give designers the
extra flexibility they need to increase circuit board den-
sity. International Rectifier has engineered the LCC pack-
age to meet the specific needs of the power market by
increasing the size of the bottom source pad, thereby
enhancing the thermal and electrical performance. The
lid of the package is grounded to the source to reduce
RF interference.
Absolute Maximum Ratings
ID @ VGS = 10V, TC = 25°C
ID @ VGS = 10V, TC = 100°C
IDM
PD @ TC = 25°C
Parameter
Continuous Drain Current
Continuous Drain Current
Pulsed Drain Current
Max. Power Dissipation
Linear Derating Factor
VGS
EAS
IAR
EAR
dv/dt
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
TJ
TSTG
Operating Junction
Storage Temperature Range
Pckg. Mounting Surface Temp.
Weight
For footnotes refer to the last page
www.irf.com
LCC-18
Features:
! Surface Mount
! Small Footprint
! Alternative to TO-39 Package
! Hermetically Sealed
! Dynamic dv/dt Rating
! Avalanche Energy Rating
! Simple Drive Requirements
! Light Weight
1.8
1.1
7.2
14
0.11
±20
0.185
-
-
4.0
-55 to 150
300 (for 5 S)
0.42(typical)
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
oC
g
1
1/16/01

1 page




IRFE320 pdf
Fig 9. Maximum Drain Current Vs.
Case Temperature
IRFE320
VDS
VGS
RG
RD
D.U.T.
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
+-V D D
Fig 10a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on) tr
td(off) tf
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
www.irf.com
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