|
|
PDF ISL9206 Data sheet ( Hoja de datos )
| Número de pieza | ISL9206 | |
| Descripción | FlexiHash | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL9206 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
®
Data Sheet
March 9, 2006
ISL9206
FN9260.0
FlexiHash+™ For Battery Authentication
The ISL9206 is a highly cost-effective fixed-secret hash
engine based on Intersil’s second generation FlexiHash™
technology. The device authentication is achieved through a
challenge-response scheme customized for low-cost
applications, where cloning via eves-dropping without
knowledge of the device’s secret code is not economically
viable. When used for its intended applications, the ISL9206
offers the same level of effectiveness as other significantly
more expensive high maintenance monetary-grade hash
algorithm and authentication schemes.
The ISL9206 has a wide operating voltage range, and is
suitable for direct powering from a 1-cell Li-Ion/Li-Poly or a
3-cell series NiMH battery pack. The ISL9206 can also be
powered by the XSD bus when the bus pull-up voltage is
3.3V or higher. The device connects directly to the cell
terminals of a battery pack, and includes on-chip voltage
regulation circuit, POR, and a non-crystal based oscillator for
bus timing reference.
Communication with the host is achieved through a single-
wire XSD interface - a light-weight subset of Intersil’s ISD bus
interface. The XSD bus is compatible for use with serial ports
offered by all 8250 compatible UART’s or a single GPIO
(general purpose input and output) pin of a microprocessor.
A clone prevention solution utilizing the ISL9206 offers
safety and revenue protection at the lowest cost and power,
and is suitable for protection against after-market
replacement for a wide variety of low-cost applications.
Ordering Information
PART #
(NOTE)
PART
TEMP.
PACKAGE PKG.
MARKING RANGE (°C) (Pb-Free) DWG. #
ISL9206DHZ-T 206Z
-20 to +85 5 Ld SOT23-5 P5.064
Tape and Reel
ISL9206EVAL1 ISL9206 Evaluation Kit
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinout
ISL9206 (SOT23-5)
TOP VIEW
VSS 1
5 XSD
N/C 2
VDD 3
4 TIO
Features
• Challenge-response based authentication scheme using
32-bit challenge code and 8-bit authentication code
• Fast and flexible authentication process. Multi-pass
authentication can be used to achieve the highest security
level if necessary
• 16x8 OTP ROM stores up to three sets of 32-bit host-
selectable secrets with additional programmable memory
for storage of up to 48 bits of ID code and/or pack
information
• FlexiHash+ engine uses two sets of 32-bit secrets for
authentication code generation
• Non-unique mapping of the secret key to an 8-bit
authentication code maximizes hacking difficulty due to
need for exhaustive key search (superior to SHA-1)
• Supports 1-cell Li-Ion/Li-Poly and 3-cell series NiMH
battery packs (2.6V ~ 4.8V operation), or powered by the
XSD bus
• XSD single-wire host bus interface communicates with all
8250-compatible UART’s or a single GPIO. Supports CRC
on read data and transfer bit-rate up to 23kbps
• True “Zero Power” sleep mode - automatically entered
after a bus inactivity time-out period
• 5 Ld SOT-23 package
• -20°C to +85°C operating temperature range
• Pb-free plus anneal available (RoHS compliant)
Applications
• Battery pack authentication
• Printer cartridges
• Add-on accessories
• Other non-monetary authentication applications
Related Literature
• Application Note AN1237 “ISL9206 Evaluation Kit”
• Application Note AN1167 “Implementing XSD Host Using
a GPIO”
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
FlexiHash is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
1 page  
ISL9206
Theory of Operation
The ISL9206 contains all circuitry required to support battery
pack authentication based on a challenge-response
scheme. It provides a 16-byte One-Time Programmable
Read-Only Memory (OTPROM) space for the storage of up
to 96-bit of secret for the authentication and other user
information. A 32-bit hash engine (FlexiHash+™) calculates
the authentication result immediately after receiving a 32-bit
random challenge code. The communication between the
ISL9206 and the host is implemented through the XSD
single-wire communication bus.
Major functions within the ISL9206 include the following, as
shown in Figure 3.
• Power-on reset (POR) and a 2.5V regulator to power all
internal logic circuits.
• 16 x 8-Bit (16-Byte) OTP ROM as shown in Table 8. The
first part (two bytes) contains the device default
configuration (DCFG) information (such as the device
address and the XSD communication speed) and the
default trimming (DTRM) information (such as the internal
oscillator frequency trimming). The second part contains
two groups (12-byte) of memory that can be independently
locked out for the storage of up to three sets of secret. The
last part provides two additional bytes of space for
general-purpose information.
• Control functions, including master control (MSCR) and
status (STAT) registers (as shown in Table 9), interrupt
generation, and the test-related interface.
• FlexiHash+™ engine that includes the 32-bit highly non-
linear proprietary hash engine, secret selection register,
challenge code register, and the authentication result
register. Table 10 shows all the registers.
• XSD communication bus Interface. The XSD device
address and the communication speed are configured in
the DCFG address in the OTPROM, as given in Table 8.
• Time Base Reference.
The following explain in detail the operation of the ISL9206.
Power-On Reset (POR)
The ISL9206 powers up in Sleep mode. It remains in Sleep
mode until a power-on ‘break’ command is received from the
host through the XSD bus. The initial power-on ’break’ can
be of any pulse width as long as it is wider than the XSD
input deglitch time (20µs). Once the ‘break’ command is
received, the internal regulator is powered up. About 20µs
after the falling edge of the power-on ‘break’, an internal
POR circuit releases the reset to the digital block, and a
POR sequence is started. During the POR sequence, the
ISL9206 initializes itself by loading the default device
configuration information from pre-assigned locations within
the OTP ROM memory. After initialization, a ‘break’
command is returned to the host to indicate that the ISL9206
is ready and waiting for a bus transaction from the host.
Host Break
Device Break
XSD Bus
Waveform
60 µs
TYP
1.391
BTD
(A) When the Host Power-on Break is Wider Than 60µs.
Host Break
Device Break
XSD Bus
Waveform
(B) When the Host Power-on Break is Narrower Than 60µs.
FIGURE 4. POWER-ON BREAK SIGNAL TO WAKE-UP THE
ISL9206 FROM SLEEP MODE
Note that the ISL9206 will initiate the power-on sequence
without waiting for the power-on ‘break’ signal to return to
the high state. If the host sends an initial ‘break’ pulse wider
than 60µs, the device-ready ‘break’ returned by the ISL9206
will likely be merged with the pulse sent by the host and,
therefore, may not be detectable. Figure 4 illustrates the
waveforms during the Power-on Reset. Figure 4 (A) is for the
case that the power-on ‘break’ rising edge occurs after the
device starts to sending the ‘break’. Figure 4 (B) shows the
case that the power-on ‘break’ finishes before the device
sending its ‘break’. The device break signal is always 1.391
times of the device bit-time (BT, see XSD Bus Interface
section for more details). Either case in Figure 4 will wake up
the device successfully if the device is in the sleep mode.
It is important to keep in mind that a narrow ‘break’ signal will
be taken as a normal bit signal and cause errors, if the
device is not in the sleep mode. For this reason, the narrow
power-on ‘break’ signal should be used only if the user has
to see the returned ‘break’ signal.
Auto-Sleep
While the ISL9206 is powered up and there is no bus activity
for more than about 1 second, the device will automatically
return to Sleep mode. Sleep mode can be entered
independent of whether the XSD bus is held high or low.
While the ISL9206 is in Sleep mode, it is recommended that
the XSD bus be held low to eliminate current drain through
the XSD-pin internal pull-down current.
Auto-Sleep mode can be disabled by clearing the ASLP bit
in the MSCR register. By default, Auto-Sleep is always
enabled at power-up and after a soft reset. Auto-sleep
function can be permanently disabled by clearing the 0-00[2]
bit (the ASLP bit in DCFG) during OTP ROM programming.
5 FN9260.0
March 9, 2006
5 Page 
ISL9206
Bus Transaction Protocol
The XSD bus for the ISL9206 defines three types of bus
transactions. Figure 10 shows the bus transaction protocol.
The blue color represents the signal sent by the host and the
green color stands for the signal sent by the device. Before
the transaction starts, the host should make sure that the
XSD device is not in the sleep mode. One method is to
always send a ‘break’ signal before starting the transaction,
as shown in Figure 10. If the device is not in the sleep mode,
the ‘break’ signal is not mandatory. The ‘break’ pulse width
may appear to be wider than what the host sends out
because of the reason explained in Figure 4. The symbols in
Figure 10 are explained in Table 7.
TABLE 7. SYMBOLS IN THE BUS TRANSACTION PROTOCOL
SYM
DESCRIPTION
MIN TYP MAX
IFGH Host inter-frame gap
IFGD Device inter-frame gap
TAH Host turn-around time
TAD Device turn-around time
0 BTH
800ms
1 BTD
1 BTH
800ms
1 BTD
Passive CRC Support
The CRC feature only supports the read transaction in the
ISL9206. When the OPCODE in the instruction is ‘10’, an
8-bit CRC is automatically calculated for the data bytes
being transferred out. The CRC result is then appended after
the last data byte is read out.
CRC is generated using the DOW CRC polynomial as
follows:
Polynom = 1 + X4 + X5 + X8
The CRC generation algorithm is logically illustrated in
Figure 11. Prior to a new CRC calculation, the LFSR (linear
feedback shift register) is initialized to zero. The read data to
be transmitted out is concurrently shifted into the CRC
calculator. After the actual data is transmitted out, the final
content of the LFSR is the resulting CRC value. This value is
transmitted out after the read data, with LSB being
transmitted out first.
(A) Multi-Byte Write Instruction.
break TSD
Write Instruction Frame
IFGH
Data Frame 1
IFGH Data Frame 2
(B) Multi-Byte Read Instruction.
break TSD
Read Instruction Frame
TA D
Data Frame 1
(output from slave)
IFG D
Data Frame 2
(output from slave)
(C) Back-to-Back Transaction (Read Followed by Write).
break TSD
Read Instruction Frame
TA D
Data Frame
(output from slave)
TA H
Next Instruction
Frame
FIGURE 10. XSD BUS TRANSACTION PROTOCOL. THE ‘BREAK’ SIGNAL IS OPTIONAL IF THE DEVICE IS AWAKE
SSeerriiaal
DOautaput
1st
Stage
LSB
2nd
Stage
3rd
Stage
4th
Stage
5th
Stage
6th
Stage
7th
Stage
FIGURE 11. THE CRC CALCULATOR FOR THE PASSIVE CRC SUPPORT
8th
Stage
MSB
11 FN9260.0
March 9, 2006
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISL9206.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL9200 | Charging System Safety Circuit | Intersil Corporation |
| ISL9201 | Li-ion Battery Charger | Intersil Corporation |
| ISL9203 | Li-ion/Li Polymer Battery Charger | Intersil Corporation |
| ISL9203A | Li-ion/Li Polymer Battery Charger | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |