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PDF UPD8872 Data sheet ( Hoja de datos )
| Número de pieza | UPD8872 | |
| Descripción | CCD LINEAR IMAGE SENSOR | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD8872
(5400 + 5400) PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The µ PD8872 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The µ PD8872 has 3 rows of (5400 + 5400) staggered pixels, and each row has a dual-sided readout-type charge
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
1200 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
• Valid photocell : (5400 + 5400) staggered pixels × 3
• Photocell pitch : 5.25 µ m
• Line spacing : 63 µ m (12 lines) Red line - Green line, Green line - Blue line
• Color filter
10.5 µ m (2 lines) Odd line - Even line (for each color)
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
• Resolution
: 48 dot/mm A4 (210 × 297 mm) size (shorter side)
1200 dpi US letter (8.5” × 11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
: 10 MHz Max.
• Power supply : +12 V
• On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
µ PD8872CY
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15330EJ3V0DS00 (3rd edition)
Date Published July 2003 NS CP (K)
Printed in Japan
The mark shows major revised points.
1 page  
µ PD8872
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Symbol
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp clock
voltage
VOD
Vφ 1, Vφ 2, Vφ 1L, Vφ 2L
Vφ RB
Vφ CLB
Transfer gate clock voltage
Operating ambient temperatureNote
Vφ TG1 to Vφ TG3
TA
Storage temperature
Tstg
Note Use at the condition without dew condensation.
Ratings
−0.3 to +15
−0.3 to +8
−0.3 to +8
−0.3 to +8
−0.3 to +8
0 to +60
−40 to +70
Unit
V
V
V
V
V
°C
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output drain voltage
Shift register clock high level
Shift register clock low level
VOD
Vφ 1_H, Vφ 2_H, Vφ 1LH, Vφ 2LH
Vφ 1_L, Vφ 2_L, Vφ 1LL, Vφ 2LL
11.4
4.75
−0.3
12.0
5.0
0
12.6
5.5
+0.25
V
V
V
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock
high level
Vφ RBH
Vφ RBL
Vφ CLBH
4.5 5.0 5.5 V
−0.3 0 +0.5 V
4.5 5.0 5.5 V
Reset feed-through level clamp clock
low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
Vφ CLBL
Vφ TG1H to Vφ TG3H
Vφ TG1L to Vφ TG3L
fφ RB
−0.3
4.75
−0.3
−
0
Vφ1_
Note
H
0
2.0
+0.5
Vφ
Note
1_H
+0.15
10.0
V
V
V
MHz
Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1_H),
Image lag can increase.
Data Sheet S15330EJ3V0DS
5
5 Page 
TIMING CHART 3 (Line clamp mode, for each color)
t1
φ1
φ2
φ 1L
φ 2L
φ RB
t5 t3 t6
90%
10%
90%
10%
90%
10%
t1'
90%
10%
90%
10%
t4
"H"
φ CLB
VOUT
RFTN
td
RFTN
10%
µ PD8872
t2
t2'
t5 t3 t6
t4
td
VOS
Symbol
Min.
Typ.
Max.
Unit
t1, t2
0 25 − ns
t1’, t2’
0 5 − ns
t3
20 100
−
ns
t4
30 150
−
ns
t5, t6
0 25 − ns
Data Sheet S15330EJ3V0DS
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet UPD8872.PDF ] | |
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