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Datasheet MC74HC14A PDF ( 特性, スペック, ピン接続図 )

部品番号 MC74HC14A
部品説明 HEX Schmitt-Trigger Inverter High-Performance Silicon-Gate CMOS
メーカ Motorola
ロゴ Motorola ロゴ 
プレビュー
Total 8 pages
		
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MC74HC14A Datasheet, MC74HC14A PDF,ピン配置, 機能
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex Schmitt-Trigger Inverter
High–Performance Silicon–Gate CMOS
The MC54/74HC14A is identical in pinout to the LS14, LS04 and the
HC04. The device inputs are compatible with Standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC14A is useful to “square up” slow input rise and fall times. Due
to hysteresis voltage of the Schmitt trigger, the HC14A finds applications
in noisy environments.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 60 FETs or 15 Equivalent Gates
LOGIC DIAGRAM
1
A1
2
Y1
3
A2
4
Y2
5
A3
9
A4
11
A5
6
Y3
Y=A
8
Y4 Pin 14 = VCC
Pin 7 = GND
10
Y5
13
A6
12
Y6
MC54/74HC14A
14
1
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
ORDERING INFORMATION
MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Ceramic
Plastic
SOIC
TSSOP
FUNCTION TABLE
Inputs
Outputs
AY
LH
HL
Pinout: 14–Lead Packages (Top View)
VCC A6 Y6 A5 Y5 A4 Y4
14 13 12 11 10 9 8
1234567
A1 Y1 A2 Y2 A3 Y3 GND
10/95
© Motorola, Inc. 1995
1
REV 7

1 Page



MC74HC14A pdf, ピン配列
MC54/74HC14A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
VCC
Guaranteed Limit
V –55 to 25°C 85°C 125°C Unit
VT+ max
Maximum Positive–Going Input
Threshold Voltage
(Figure 3)
Vout = 0.1V
|Iout| 20µA
2.0
1.50
1.50 1.50
V
3.0 2.15 2.15 2.15
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VT+ min
Minimum Positive–Going Input
Threshold Voltage
(Figure 3)
Vout = 0.1V
|Iout| 20µA
2.0
1.0
0.95 0.95
V
3.0 1.5 1.45 1.45
4.5 2.3 2.25 2.25
6.0 3.0 2.95 2.95
VT– max
Maximum Negative–Going Input
Threshold Voltage
(Figure 3)
Vout = VCC – 0.1V
|Iout| 20µA
2.0
0.9
0.95 0.95
V
3.0 1.4 1.45 1.45
4.5 2.0 2.05 2.05
6.0 2.6 2.65 2.65
VT– min
Minimum Negative–Going Input
Threshold Voltage
(Figure 3)
Vout = VCC – 0.1V
|Iout| 20µA
2.0 0.3
3.0 0.5
4.5 0.9
6.0 1.2
0.3 0.3 V
0.5 0.5
0.9 0.9
1.2 1.2
VHmax
Note 2
Maximum Hysteresis Voltage
(Figure 3)
Vout = 0.1V or VCC – 0.1V
|Iout| 20µA
2.0
1.20
1.20 1.20
V
3.0 1.65 1.65 1.65
4.5 2.25 2.25 2.25
6.0 3.00 3.00 3.00
VHmin
Note 2
Minimum Hysteresis Voltage
(Figure 3)
Vout = 0.1V or VCC – 0.1V
|Iout| 20µA
2.0
0.20
0.20 0.20
V
3.0 0.25 0.25 0.25
4.5 0.40 0.40 0.40
6.0 0.50 0.50 0.50
VOH
Minimum High–Level Output
Voltage
Vin VT– min
|Iout| 20µA
2.0 1.9
4.5 4.4
6.0 5.9
1.9 1.9 V
4.4 4.4
5.9 5.9
VOL
Maximum Low–Level Output
Voltage
Vin VT– min
|Iout| 2.4mA 3.0
2.48
2.34 2.20
|Iout| 4.0mA 4.5 3.98 3.84 3.70
|Iout| 5.2mA 6.0 5.48 5.34 5.20
Vin VT+ max
|Iout| 20µA
2.0 0.1
4.5 0.1
6.0 0.1
0.1 0.1 V
0.1 0.1
0.1 0.1
Vin VT+ max |Iout| 2.4mA 3.0 0.26 0.33 0.40
|Iout| 4.0mA 4.5 0.26 0.33 0.40
|Iout| 5.2mA 6.0 0.26 0.33 0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0µA
6.0 1.0
10 40 µA
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
2. VHmin > (VT+ min) – (VT– max); VHmax = (VT+ max) – (VT– min).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA


3Pages


MC74HC14A 電子部品, 半導体
MC54/74HC14A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
-A-
14 8
-B-
17
C
-T-
SEATING
PLANE
F
GN
D 14 PL
0.25 (0.010) M T A S
K
L
M
J 14 PL
0.25 (0.010) M T B S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
C 0.155 0.200 3.94 5.08
D 0.015 0.020 0.39 0.50
F 0.055 0.065 1.40 1.65
G 0.100 BSC
2.54 BSC
J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC
7.62 BSC
M 0° 15° 0° 15°
N 0.020 0.040 0.51 1.01
14
1
A
F
HG
8
B
7
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
C
N
SEATING
PLANE
D
K
L
J
M
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
A 0.715 0.770
B 0.240 0.260
C 0.145 0.185
D 0.015 0.021
F 0.040 0.070
G 0.100 BSC
H 0.052 0.095
J 0.008 0.015
K 0.115 0.135
L 0.300 BSC
M 0_ 10_
N 0.015 0.039
MILLIMETERS
MIN MAX
18.16 19.56
6.10 6.60
3.69 4.69
0.38 0.53
1.02 1.78
2.54 BSC
1.32 2.41
0.20 0.38
2.92 3.43
7.62 BSC
0_ 10_
0.39 1.01
MOTOROLA
6 High–Speed CMOS Logic Data
DL129 — Rev 6

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