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PDF HD74SSTV16857 Data sheet ( Hoja de datos )
| Número de pieza | HD74SSTV16857 | |
| Descripción | 1:1 14-bit SSTL-2 Registered Buffer | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74SSTV16857
1:1 14-bit SSTL_2 Registered Buffer
ADE-205-336F (Z)
Rev.6
June. 2001
Description
The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and
LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is
triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to
maintain noise margins. When RESET is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held
in the low state during power up.
Features
• Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input
• Differential SSTL_2 (Stub series terminated logic) CLK signal
• Flow through architecture optimizes PCB layout
• Package type
Package type
TSSOP-48 pin
TVSOP-48 pin
Package code
TTP-48DB
TTP-48DEV
Package suffix
T
N
Taping code
EL (1,000 pcs / Reel)
EL (1,000 pcs / Reel)
1 page  
HD74SSTV16857
Recommended Operating Conditions
Item
Symbol Min
Typ Max
Unit Conditions
Supply voltage
Output supply voltage
Reference voltage
Termination voltage
Input voltage
AC high level input voltage
AC low level input voltage
DC high level input voltage
DC low level input voltage
High level input voltage
Low level input voltage
Differential (Common mode range)
input voltage (Minimum peak to
peak input)
VCC
VDDQ
V
REF
V
TT
VI
VIH
VIL
VIH
V
IL
V
IH
VIL
VCMR
VPP
VDDQ
2.3
2.5
2.5
1.15 1.25
V –40 mV
REF
0
V
REF
—
VREF+310 mV —
——
VREF+150 mV —
——
1.7 —
–0.3 —
0.97 —
360 —
2.7 V
2.7 V
1.35
V +40 mV
REF
VCC
—
V
V
V
V
V
REF
=
0.5
×
V
DDQ
D
VREF–310 mV V
—V
D
D
V –150 mV
REF
V +0.3
DDQ
0.7
V
V
V
D
RESET
RESET
1.53 V CLK, CLK
— mV CLK, CLK
High level output current
Low level output current
Operating temperature
IOH —
IOL —
Ta 0
— –20
— 20
— 70
mA
mA
°C
Note: The RESET input of the device must be held at VDDQ or GND to ensure proper device operation. The
differential inputs must not be floating, unless RESET is low.
Rev.6, Jun. 2001, page 5 of 15
5 Page 
HD74SSTV16857
Waveforms – 4
LVCMOS
RESET
Input
VCC /2
tPHL
VIH
VIL
Output
Notes:
1.
2.
3.
4.
5.
6.
7.
VOH
VTT
VOL
ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
The outputs are measured one at a time with one transition per measurement.
V = V = V /2
TT REF DDQ
VIH = VREF+310 mV (AC voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
VIL = VREF–310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
t and t are the same as t
PLH PHL
pd
Rev.6, Jun. 2001, page 11 of 15
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HD74SSTV16857.PDF ] | |
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