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PDF HT48R502 Data sheet ( Hoja de datos )
| Número de pieza | HT48R502 | |
| Descripción | I/O Type 8-Bit OTP MCU | |
| Fabricantes | Holtek Semiconductor | |
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HT48R502
I/O Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0013E HT48 & HT46 LCM Interface Design
- HA0021E Using the I/O Ports on the HT48 MCU Series
- HA0055E 2^12 Decoder (8+4 - Corresponds to HT12E)
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Low voltage reset function
· 56 bidirectional I/O lines (max.)
· 1 interrupt input
· 2´16-bit programmable timer/event counter and
overflow interrupts
· On-chip RC oscillator, external crystal and RC oscil-
lator
· 32768Hz crystal oscillator for timing purposes only
· Watchdog Timer
· 4096´15 program memory ROM
· 224´8 data memory RAM
· Buzzer driving pair and PFD supported
· HALT function and wake-up feature reduce power
consumption
· 16-level subroutine nesting
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· Bit manipulation instruction
· 15-bit table read instruction
· 63 powerful instructions
· All instructions in one or two machine cycles
· 48-pin SSOP, 64-pin QFP package
General Description
The HT48R502 is an 8-bit high performance, RISC ar-
chitecture microcontroller devices specifically designed
for multiple I/O control product applications.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, Watchdog Timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Rev. 1.00
1 September 27, 2006
1 page  
www.DataSheet4U.com
HT48R502
Symbol
Parameter
Test Conditions
VDD Conditions
Min. Typ. Max. Unit
3V ¾ ¾ 5 mA
ISTB3 Standby Current (WDT Disabled, RTC On)
No load, system HALT
5V ¾ ¾ 10 mA
VIL1 Input Low Voltage for I/O Ports
¾¾
0 ¾ 0.3VDD V
VIH1 Input High Voltage for I/O Ports ¾ ¾ 0.7VDD ¾ VDD V
VIL2 Input Low Voltage (RES)
¾¾
0 ¾ 0.4VDD V
VIH2 Input High Voltage (RES)
¾ ¾ 0.9VDD ¾ VDD V
VLVR Low Voltage Reset
¾ LVR enabled
2.7 3.0 3.3
V
IOL I/O Port Sink Current
3V VOL=0.1VDD
5V VOL=0.1VDD
4 8 ¾ mA
10 20 ¾ mA
IOH I/O Port Source Current
3V VOH=0.9VDD
5V VOH=0.9VDD
-2 -4 ¾ mA
-5 -10 ¾ mA
RPH Pull-high Resistance
3V
¾
5V
20 60 100 kW
10 30 50 kW
A.C. Characteristics
Ta=25°C
Symbol
Parameter
fSYS1 System Clock (Crystal OSC, RC OSC)
Test Conditions
VDD Conditions
¾ 2.2V~5.5V
¾ 3.3V~5.5V
Min. Typ. Max. Unit
400 ¾ 4000 kHz
400 ¾ 8000 kHz
3.2MHz
1800 ¾ 5400 kHz
fSYS2 System Clock (Internal RC OSC)
1.6MHz
5V
800kHz
900 ¾ 2700 kHz
450 ¾ 1350 kHz
400kHz
225 ¾ 675 kHz
fTIMER Timer I/P Frequency (TMR)
¾ 2.2V~5.5V
¾ 3.3V~5.5V
0 ¾ 4000 kHz
0 ¾ 8000 kHz
tWDTOSC Watchdog Oscillator Period
3V ¾
5V ¾
45
32
tWDT1
Watchdog Time-out Period (WDT OSC)
3V 11
Without WDT prescaler
5V 8
tWDT2 Watchdog Time-out Period (System Clock) ¾ Without WDT prescaler ¾
tWDT3 Watchdog Time-out Period (RTC OSC) ¾ Without WDT prescaler ¾
tRES External Reset Low Pulse Width
¾
¾
1
tSST System Start-up Timer Period
¾ Wake-up from HALT
¾
tINT Interrupt Pulse Width
¾¾
1
tLVR Low Voltage Width to Reset
¾¾
0.25
90
65
23
17
1024
7.812
¾
1024
¾
1
180
130
46
33
¾
¾
¾
¾
¾
2
ms
ms
ms
ms
tSYS
ms
ms
tSYS
ms
ms
Note: tSYS=1/fSYS
Rev. 1.00
5 September 27, 2006
5 Page 
www.DataSheet4U.com
HT48R502
32768Hz crystal oscillator (RTC OSC). Also, the fre-
quencies of the internal RC oscillator can be 3.2MHz,
1.6MHz, 800kHz and 400kHz (depends on the options).
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 65ms at 5V. The WDT oscilla-
tor can be disabled by options to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), RTC clock or instruction
clock (system clock divided by 4), determines the op-
tions. This timer is designed to prevent a software mal-
function or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by options. If the Watchdog Timer
is disabled, all the executions related to the WDT result
in no operation. The RTC clock is enabled only in the in-
ternal RC+RTC mode.
Once the internal WDT oscillator (RC oscillator with a
period of 65ms at 5V normally) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out pe-
riod of 17ms at 5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.1s at 5V
seconds. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and oper-
ates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting pur-
pose. In this situation the logic can only be restarted by
external logic. The high nibble and bit 3 of the WDTS are
reserved for users defined flags, which can be used to
indicate some specified status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) or 32kHz crystal oscil-
lator (RTC OSC) is strongly recommended, since the
HALT will stop the system clock.
WS2
0
0
0
0
1
1
1
1
WS1 WS0
Division Ratio
00
01
10
11
00
01
10
11
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
WDTS (09H) Register
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset² and only
the Program Counter and SP are reset to zero. To clear
the contents of WDT (including the WDT prescaler),
three methods are adopted; external reset (a low level to
RES), software instruction and a ²HALT² instruction.
The software instruction include ²CLR WDT² and the
other set - ²CLR WDT1² and ²CLR WDT2². Of these
two types of instruction, only one can be active depend-
ing on the option - ²CLR WDT times selection option². If
the ²CLR WDT² is selected (i.e. CLRWDT times equal
one), any execution of the ²CLR WDT² instruction will
clear the WDT. In the case that ²CLR WDT1² and ²CLR
WDT2² are chosen (i.e. CLRWDT times equal two),
these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip as a result
of time-out.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
· The contents of the on chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
S y s te m C lo c k /4
R TC O SC
W DT
O SC
O p tio n
S e le c t
8 - b it C o u n te r
Watchdog Timer
W D T P r e s c a le r
7 - b it C o u n te r
8 -to -1 M U X
W D T T im e - o u t
W S 0~W S 2
Rev. 1.00
11 September 27, 2006
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT48R502.PDF ] | |
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