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UT54ACTS109 の電気的特性と機能

UT54ACTS109のメーカーはAeroflex Circuit Technologyです、この部品の機能は「Radiation-Hardened Dual J-K Flip-Flops」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT54ACTS109
部品説明 Radiation-Hardened Dual J-K Flip-Flops
メーカ Aeroflex Circuit Technology
ロゴ Aeroflex Circuit Technology ロゴ 




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UT54ACTS109 Datasheet, UT54ACTS109 PDF,ピン配置, 機能
www.DataSheet4U.com
UT54ACS109/UT54ACTS109
Radiation-Hardened
Dual J-K Flip-Flops
FEATURES
• radiation-hardened CMOS
- Latchup immune
• High speed
• Low power consumption
• Single 5 volt supply
• Available QML Q or V processes
• Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS109 and the UT54ACTS109 are dual J-K posi-
tive triggered flip-flops. A low level at the preset or clear inputs
sets or resets the outputs regardless of the other input levels.
When preset and clear are inactive (high), data at the J and K
input meeting the setup time requirements are transferred to the
outputs on the positive-going edge of the clock pulse. Following
the hold time interval, data at the J and K input can be changed
without affecting the levels at the outputs. The flip-flops can
perform as toggle flip-flops by grounding K and tying J high.
They also can perform as D flip-flops if J and K are tied together.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
PRE
L
H
L
H
H
H
H
H
INPUTS
CLR
CLK
HX
LX
LX
H
H
H
H
HL
OUTPUT
JK Q
Q
XX H
L
XX
L
H
X X H1 H1
LL
L
H
HL
Toggle
L H No Change
HH H
L
X X No Change
Note:
1. The output levels in this configuration are not guaranteed to meet the mini-
mum levels for VOH if the lows at preset and clear are near VIL maximum. In
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
PINOUTS
16-Pin DIP
Top View
CLR1
J
K1
CLK1
PRE1
Q1
Q1
VSS
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
CLR1
J1
K1
CLK1
PRE1
Q1
Q1
VSS
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
LOGIC SYMBOL
PRE1
J1
CLK1
K1
CLR1
(5)
(2)
(4)
(3)
(1)
S
J1
C1
K1
R
(6) Q1
(7)
Q1
(11)
PRE2
(14)
J2
(12)
CLK2
(13)
K2
(15)
CLR2
(10)
Q2
(9) Q2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
61 RadHard MSI Logic

1 Page





UT54ACTS109 pdf, ピン配列
UT54ACS109/UT54ACTS109
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VDD
VIN
TC
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to VDD
-55 to + 125
UNITS
V
V
C
63 RadHard MSI Logic


3Pages


UT54ACTS109 電子部品, 半導体
UT54ACS109/UT54ACTS109
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C)
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
tPHL CLK to Q, Q
5 27
tPLH CLK to Q, Q
4 23
tPLH PRE to Q
1 16
tPHL PRE to Q
1 19
tPHL CLR to Q
2 19
tPLH CLR to Q
2 16
fMAX Maximum clock frequency
62
tSU1 PRE or CLR inactive
Setup time before CLK
5
tSU2 Data setup time before CLK
5
tH3 Data hold time after CLK
3
tW Minimum pulse width
PRE or CLR low
CLK high
CLK low
8
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested.
UNIT
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
RadHard MSI Logic
66

6 Page



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共有リンク

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UT54ACTS10

Triple 3-Input NAND Gates

Aeroflex Circuit Technology
Aeroflex Circuit Technology
UT54ACTS109

Radiation-Hardened Dual J-K Flip-Flops

Aeroflex Circuit Technology
Aeroflex Circuit Technology


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