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PDF AD6654 Data sheet ( Hoja de datos )
| Número de pieza | AD6654 | |
| Descripción | 4-/6-Channel Wideband IF to Baseband Receiver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
SNR = 90 dB in 1.25 MHz bandwidth to Nyquist
SNR = 87 dB in 1.25 MHz bandwidth to 200 MHz
Integrated 14-bit, 92.16 MSPS ADC
IF sampling frequencies to 200 MHz
Internal 2.4 V reference, 2.2 V p-p analog input range
Internal differential track-and-hold analog input
Processes 4/6 wideband carriers simultaneously
Fractional clock multiplier to 200 MHz
Programmable decimating FIR filters, interpolating
half-band filters and programmable AGC loops
with 96 dB range
Three 16-bit configurable parallel output ports
User-configurable built-in self-test (BIST) capability
8-/16-bit microport and SPORT/SPI® serial port control
14-Bit, 92.16 MSPS, 4-/6-Channel
Wideband IF to Baseband Receiver
AD6654
APPLICATIONS
Multicarrier, multimode digital receivers
GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000,
TD-SCDMA, WiMAX
Micro and pico cell systems, software radios
Wireless local loop
Smart antenna systems
In-building wireless telephony
Broadband data applications
Instrumentation and test equipment
FUNCTIONAL BLOCK DIAGRAM
14-BIT ADC FRONT END
4-CHANNEL AND 6-CHANNEL DIGITAL DOWN CONVERTER
ENC+
ENC–
AIN+
AIN–
VREF
SHA
INTERNAL
TIMING
ADC
14
INPUT
MATRIX
2.4V
VREF
NCO
NCO
NCO
CIC5
M = 1–32
CIC5
M = 1–32
CIC5
M = 1–32
FIR1
HB1
M = BYP, 2
FIR1
HB1
M = BYP, 2
FIR1
HB1
M = BYP, 2
FIR2
HB2
M = BYP, 2
FIR2
HB2
M = BYP, 2
FIR2
HB2
M = BYP, 2
MRCF
DRCF
M = 1–16
MRCF
DRCF
M = 1–16
MRCF
DRCF
M = 1–16
CRCF
M = 1–16
CRCF
M = 1–16
CRCF
M = 1–16
OVR
(ADC OVERRANGE)
EXP
3
(VGA LEVEL CONTROL)
PRN
GEN
EXP
BITS
PEAK/
RMS
MSMT
NCO
NCO
CIC5
M = 1–32
CIC5
M = 1–32
FIR1
HB1
M = BYP, 2
FIR1
HB1
M = BYP, 2
FIR2
HB2
M = BYP, 2
FIR2
HB2
M = BYP, 2
MRCF
DRCF
M = 1–16
MRCF
DRCF
M = 1–16
CRCF
M = 1–16
CRCF
M = 1–16
(AVAILABLE IN
6-CHANNEL MODEL ONLY)
NCO
CIC5
M = 1–32
FIR1
HB1
M = BYP, 2
FIR2
HB2
M = BYP, 2
MRCF
DRCF
M = 1–16
CRCF
M = 1–16
M = DECIMATION
L = INTERPOLATION
AVDD, DRVDD,
VDDCORE, VDDIO, GND
SYNC
0, 1, 2, 3
CLOCK
MULTIPLIER
8-BIT/16-BIT MICROPORT
INTERFACE
LHB
L = 1, 2
LHB
L = 1, 2
LHB
L = 1, 2
LHB
L = 1, 2
LHB
L = 1, 2
PA
AGC PB
PC
LHB
L = 1, 2
SPORT/
SPI INTERFACE
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.
1 page  
can perform. It can also allow complex filtering operations to be
achieved in the programmable filters.
The digital AGC provides the user with scaled digital outputs
based on the rms level of the signal present at the output of the
digital filters. The user can set the requested level and time
constant of the AGC loop for optimum performance of the
postprocessor. This is a critical function in the base station for
CDMA application, where the power level must be well
controlled going into the RAKE receivers. It has programmable
clipping and rounding control to provide different output
resolutions.
The overall filter response for the AD6654 is the composite of
all the combined filter stages. Each successive filter stage is
capable of narrower transition bandwidths, but requires a
greater number of CLK cycles to calculate the output. The
AD6654 features a fractional clock multiplier that uses the ADC
clock (which is slower than the DDC’s processing speed) to
produce a DDC master clock up to 200 MHz. This feature
allows fractional multiplication of the input clock to allow the
DDC to function at maximum speed while maintaining edge
identity to the ADC clock.
More decimation in the first filter stage minimizes overall
power consumption. Data from the device is interfaced to a
DSP/FPGA/baseband processor via high speed parallel ports
(preferred), or a DSP-compatible microprocessor interface.
The AD6654 is available in 4-channel and 6-channel versions.
The primary focus of the data sheet is on the 6-channel part.
The only difference between the 6-channel and 4-channel
devices is that, on the 4-channel version, Channel 4 and
AD6654
Channel 5 are not available (see Figure 1). The 4-channel device
has the same DDC input port features, output ports, and
memory map as the 6-channel device. On the 4-channel
version, the memory map section for Channel 4 and Channel 5
can be programmed and read back, but the two extra channels
are disabled internally.
PRODUCT HIGHLIGHTS
1. Integrated 14-bit, 92.16 MSPS ADC.
2. Track-and-hold amplifier analog input for excellent IF
sampling up to 200 MHz.
3. Four or six independent digital filtering channels.
4. RMS/peak power monitoring of the ADC data port and
96 dB range AGCs before the output ports.
5. Three programmable RAM coefficient filters, three half-
band filters, two fixed coefficient filters, and one fifth-
order CIC filter per channel.
6. Complex filtering by combining filtering capability of
multiple channels.
7. Three 16-bit parallel output ports operating at up to
200 MHz clock.
8. Blackfin®- and TigerSHARC®-compatible, 8-/16-bit
microprocessor port.
9. Synchronous serial communications port is compatible
with most serial interface standards: SPORT, SPI, and SSR.
Rev. 0 | Page 5 of 88
5 Page 
AD6654
SERIAL PORT TIMING CHARACTERISTICS
Table 9.
Parameter1, 2, 3
SERIAL PORT CLOCK TIMING REQUIREMENTS
tSCLK SCLK Period
tSCLKL
SCLK Low Time
tSCLKH
SCLK High Time
SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0)
tSSDI SDI to ↑SCLK Setup Time
tHSDI SDI to ↑SCLK Hold Time
tSSCS SCS to ↑SCLK Setup Time
tHSCS SCS to ↑SCLK Hold Time
tDSDO
↑SCLK to SDO Delay Time
SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1)
tSSDI SDI to ↑SCLK Setup Time
tHSDI SDI to ↑SCLK Hold Time
tSSRFS
SRFS to ↓SCLK Setup Time
tHSRFS
SRFS to ↓SCLK Hold Time
tSSTFS
STFS to ↓SCLK Setup Time
tHSTFS
STFS to ↓SCLK Hold Time
tSSCS SCS to ↑SCLK Setup Time
tHSCS SCS to ↑SCLK Hold Time
tDSDO
↑SCLK to SDO Delay Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V and 3.6 V.
2 CLOAD = 40 pF on all outputs, unless otherwise noted.
3 SCLK rise/fall time should be 3 ns maximum.
Min
10.0
1.60
1.60
1.30
0.40
4.12
−2.78
4.28
0.80
0.40
1.60
−0.13
1.60
−0.30
4.12
−2.76
4.29
Typ
0.5 × tSCLK
0.5 × tSCLK
Max Unit
ns
ns
ns
ns
ns
ns
ns
7.96 ns
ns
ns
ns
ns
ns
ns
ns
ns
7.95 ns
Rev. 0 | Page 11 of 88
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD6654.PDF ] | |
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