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PDF A418316 Data sheet ( Hoja de datos )

Número de pieza A418316
Descripción 256K X 16 CMOS DYNAMIC RAM
Fabricantes AMIC Technology 
Logotipo AMIC Technology Logotipo



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A418316 Series
Preliminary 256K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Document Title
256K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
July 21, 2003
Remark
Preliminary
PRELIMINARY (July, 2003,Version 0.0)
AMIC Technology, Inc.

1 page




A418316 pdf
Block Diagram
A418316 Series
OE
WE
UCAS
LCAS
A0 - A8
RAS
CAS Clock
Generator
WE Clock
Generator
OE Clock
Generator
Column
Address
Buffers
Refresh
Counter &
Controller
Row
Address
Buffers
AY0 - AY8
AX0 - AX8
Column Decoders
Sense Amplifiers
. . 512 x 16 . .
.
.
. Memory Array
512 512 x 512 x 16
.
.
.
RAS Clock
Generator
Data I/O
Buffers
I/O0
to
I/O15
VCC
VSS
Recommended Operating Conditions (Ta = 0°C to +70°C or -40°C to +85°C)
Symbol
Description
Min.
Typ.
Max.
VCC
Power Supply
4.5 5.0 5.5
VSS
Input High Voltage
0.0 0.0 0.0
VIH Input High Voltage
2.4 - VCC + 1.0
VIL Input Low Voltage
-0.5 - 0.8
Unit
V
V
V
V
Notes
1
1
1
1
PRELIMINARY (July, 2003,Version 0.0)
3
AMIC Technology, Inc.

5 Page





A418316 arduino
A418316 Series
AC Characteristics (continued) (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.4V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
Std
# Symbol
Parameter
-25 -35
Unit
Min. Max. Min. Max.
Notes
51 tOEZ Output Buffer Turn-off Delay from
OE
- 3 - 3 ns
8
52 tRASS
RAS pulse width
( C -B-R self refresh)
100 - 100 -
µs
53 tRPS RAS precharge time
( C -B-R self refresh)
44 - 62 - ns
54 tCHS CAS hold time ( C -B-R self refresh) -50 - -50 -
ns
Notes:
1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.
3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of 8
RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.
4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and
50pF, VIL (min.) GND and VIH (max.) VCC.
5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH and VIL.
6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.
7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
8. Assumes three state test load (5pF and a 500Thevenin equivalent).
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.
11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If tWCS tWCS (min.) and tWCH tWCH (min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD tRWD (min.) , tCWD
tCWD (min.) and tAWD tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
12. These parameters are referenced to UCAS and LCAS leading edge in early write cycles and to WE leading edge in
read-modify-write cycles.
13. Access time is determined by the longer of tAA or tCAC or tCPA.
14. tASC tCP to achieve tPC (min.) and tCPA (max.) values.
PRELIMINARY (July, 2003, Version 0.0)
9
AMIC Technology, Inc.

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