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PDF ISL59530 Data sheet ( Hoja de datos )

Número de pieza ISL59530
Descripción 16 x 16 Video Crosspoint
Fabricantes Intersil Corporation 
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Data Sheet
June 12, 2006
ISL59530
FN6220.1
16x16 Video Crosspoint
The ISL59530 is a 300MHz 16x16 Video Crosspoint Switch.
Each input has an integrated DC-restore clamp and an input
buffer. Each output has a fast On-Screen Display (OSD)
switch (for inserting graphics or other video) and an output
buffer. The switch is non-blocking, so any combination of
inputs to outputs can be chosen, including one channel
driving multiple outputs. The Broadcast Mode directs one
input to all 16 outputs. The output buffers can be individually
controlled through the SPI interface, the gain can be
programmed to x1 or x2, and each output can be placed into
a high impedance mode.
The ISL59530 offers a typical -3dB signal bandwidth of
300MHz. Differential gain of 0.025% and differential phase of
0.05°, along with 0.1dB flatness out to 50MHz, make the
ISL59530 suitable for many video applications.
The switch matrix configuration and output buffer gain are
programmed through an SPI/QSPI™-compatible three-wire
serial interface. The ISL59530 interface is designed to
facilitate both fast updates and initialization. On power-up, all
outputs are high impedance to avoid output conflicts.
The ISL59530 is available in a 356 ball BGA package and
specified over an extended -40°C to +85°C temperature range.
The single-supply ISL59530 can accommodate input signals
from 0V to 3.5V and output voltages from 0V to 3.8V. Each
input includes a clamp circuit that restores the input level to
an externally applied reference in AC-coupled applications.
The ISL59531 is a fully differential input version of this device.
Block Diagram
Features
• 16x16 non-blocking switch with buffered inputs and outputs
• 300MHz typical bandwidth
• 0.025%/0.05° dG/dP
• Output gain switchable x1 or x2 for each channel
• Individual outputs can be put in a high impedance state
• -90dB Isolation at 6MHz
• SPI digital interface
• Single +5V supply operation
• Pb-free plus anneal available (RoHS compliant)
Applications
• Security camera switching
• RGB routing
• HDTV routing
Ordering Information
TAPE &
PART NUMBER REEL
PACKAGE
PKG.
DWG. #
ISL59530IKZ (Note) - 356 Ld PBGA (Pb-free) V356.27x27
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
VREF
-
+
2uA
VS+ VOVERn OVERn
16
OVERLAY
INPUT
16
LOGIC
CONTROL
16 INPUTS
Power-on
Clamp
Enable
SWITCH
MATRIX
16 OUTPUTS
SDI
SCLK
SLATCH
-
+
2uA
Av Output
x1, x2 Enable
Power-on
SPI INTERFACE, REGISTER
SDO
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.

1 page




ISL59530 pdf
ISL59530
Pin Descriptions (Continued)
NAME NUMBER
DESCRIPTION
SCLK
K3 Serial data clock
SDI L3 Serial data input
SDO
G3 Serial data output. Can be tied to SDI of
another ISL59530 to enable daisy-
chaining of multiple devices.
RESET
H3 Reset input. Pull high then low to reset
device, but not needed in normal opera-
tion. Tie to ground in final application.
VSDO
D3 Power supply for SDO pin. Tie to +5V
for a 0 to 5V SDO output signal swing.
VS +5V power supply
GND
Ground
NC No Connect - Do not electrically con-
nect to anything, including ground.
5 FN6220.1
June 12, 2006

5 Page





ISL59530 arduino
Typical Performance Curves (Continued)
ISL59530
AV = 1
RL = 100
INPUT_CH 1
OUTPUT_CH1
OSC = 40mV
FIGURE 31. DIFFERENTIAL GAIN, AV = 1
AV = 1
RL = 100
INPUT_CH 1
OUTPUT_CH 1
OSC = 40mV
FIGURE 32. DIFFERENTIAL PHASE, AV = 1
AV = 1
RL = 100
INPUT_CH 1
OUTPUT_CH 1
OSC = 40mV
FIGURE 33. DIFFERENTIAL GAIN, AV = 1
AV = 1
RL = 100
INPUT_CH 1
OUTPUT_CH 1
OSC = 40mV
FIGURE 34. DIFFERENTIAL GAIN, AV = 1
AV = 2
RL = 100
INPUT_CH 01
OUTPUT_CH 15
OSC = 40mV
FIGURE 35. DIFFERENTIAL GAIN, AV = 2
AV = 2
RL = 100
INPUT_CH 01
OUTPUT_CH 15
OSC = 40mV
FIGURE 36. DIFFERENTIAL PHASE, AV = 2
11 FN6220.1
June 12, 2006

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