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UPD44325364 の電気的特性と機能

UPD44325364のメーカーはNECです、この部品の機能は「(UPD44325xx4) 36M-BIT QDRII SRAM 4-WORD BURST OPERATION」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD44325364
部品説明 (UPD44325xx4) 36M-BIT QDRII SRAM 4-WORD BURST OPERATION
メーカ NEC
ロゴ NEC ロゴ 




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UPD44325364 Datasheet, UPD44325364 PDF,ピン配置, 機能
www.DataSheet4U.com
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD44325084, 44325094, 44325184, 44325364
36M-BIT QDRTMII SRAM
4-WORD BURST OPERATION
Description
The µPD44325084 is a 4,194,304-word by 8-bit, the µPD44325094 is a 4,194,304-word by 9-bit, the µPD44325184 is a
2,097,152-word by 18-bit and the µPD44325364 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The µPD44325084, µPD44325094, µPD44325184 and µPD44325364 integrate unique synchronous peripheral
circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive
edge of K and /K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC FBGA.
Features
1.8 ± 0.1 V power supply and HSTL I/O
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Four-tick burst for reduced address frequency
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability with µs restart
User programmable impedance output
Fast clock cycle time : 3.3 ns (300 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M16784EJ1V0DS00 (1st edition)
Date Published October 2004 NS CP(K)
Printed in Japan
The mark shows major revised points.
2003

1 Page





UPD44325364 pdf, ピン配列
Pin Configurations
/××× indicates active low signal.
µPD44325084, 44325094, 44325184, 44325364
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[µPD44325084F5-EQ2]
1 2 3 4 5 6 7 8 9 10 11
A /CQ
VSS
A
/W /NW1 /K NC /R
A
A CQ
B NC NC NC A NC K /NW0 A NC NC Q3
C NC NC NC VSS A NC A VSS NC NC D3
D NC
D4
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC
H /DLL
VREF
VDDQ VDDQ
VDD
VSS
VDD
VDDQ VDDQ
VREF
ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0
M NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D0
N NC D7 NC VSS
A
A
A VSS NC NC NC
P NC NC Q7
A
A
C
A
A NC NC NC
R TDO TCK
A
A
A /C
A
A
A TMS TDI
A
D0 to D7
Q0 to Q7
/R
/W
/NW0, /NW1
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1. Refer to Package Drawing for the index mark.
2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.
Preliminary Data Sheet M16784EJ1V0DS
3


3Pages


UPD44325364 電子部品, 半導体
µPD44325084, 44325094, 44325184, 44325364
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[µPD44325364F5-EQ2]
1 2 3 4 5 6 7 8 9 10 11
A /CQ
VSS
NC
/W /BW2 /K /BW1 /R
A VSS CQ
B Q27 Q18 D18
A /BW3 K /BW0 A
D17 Q17
Q8
C D27 Q28 D19
VSS
A
NC
A
VSS D16 Q7
D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E Q29
D29
Q20 VDDQ
VSS
VSS
VSS VDDQ Q15
D6
Q6
F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
G D30
D22
Q22 VDDQ
VDD
VSS
VDD VDDQ Q13 D13
D5
H /DLL
VREF
VDDQ VDDQ
VDD
VSS
VDD
VDDQ VDDQ
VREF
ZQ
J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4
D4
K Q32
D32
Q23 VDDQ
VDD
VSS
VDD VDDQ Q12
D3
Q3
L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1
D2
N D34 D26 Q25 VSS
A
A
A VSS Q10 D9 D1
P Q35 D35 Q26
A
A
C
A
A Q9 D0 Q0
R TDO TCK
A
A
A /C
A
A
A TMS TDI
A
D0 to D35
Q0 to Q35
/R
/W
/BW0 to /BW3
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1. Refer to Package Drawing for the index mark.
2. 3A and 10A are expansion addresses: 3A for 72Mb and 10A for 144Mb.
6 Preliminary Data Sheet M16784EJ1V0DS

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UPD44325362

(UPD44325xx2) 36M-BIT QDRII SRAM 2-WORD BURST OPERATION

NEC
NEC
UPD44325364

(UPD44325xx4) 36M-BIT QDRII SRAM 4-WORD BURST OPERATION

NEC
NEC


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