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UPD44323362 の電気的特性と機能

UPD44323362のメーカーはNECです、この部品の機能は「32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD44323362
部品説明 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
メーカ NEC
ロゴ NEC ロゴ 




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UPD44323362 Datasheet, UPD44323362 PDF,ピン配置, 機能
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD44323362
32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
1M-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
Description
The µPD44323362 is a 1,048,576 words by 36 bits synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The µPD44323362 is suitable for applications which require high-speed, low voltage, high-density memory and wide
bit configuration, such as cache and buffer memory.
The µPD44323362 is packaged in a 119-pin PLASTIC BGA (Ball Grid Array).
Features
Fully synchronous operation
HSTL Input / Output levels
Fast clock access time: 2.0 ns / 250 MHz
Asynchronous output enable control: /G
Byte write control: /SBa (DQa1 to DQa9), /SBb (DQb1 to DQb9), /SBc (DQc1 to DQc9), /SBd (DQd1 to DQd9)
Common I/O using three-state outputs
Internally self-timed write cycle
Late write with 1 dead cycle between Read-Write
User-configurable outputs: Controlled impedance outputs or push-pull outputs
Boundary scan (JTAG) IEEE 1149.1 compatible
2.5 ± 0.125 V (Chip) / 1.4 to 1.9 V (I/O) supply
119 bump BGA package, 1.27 mm pitch, 14 mm × 22 mm
Sleep mode: ZZ (Enables sleep mode, active high)
Ordering Information
Part number
µPD44323362F1-C40-FJ1
Access time
2.0 ns
Clock frequency
250 MHz
Package
119-pin PLASTIC BGA
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M16379EJ4V0DS00 (4th edition)
Date Published May 2004 NS CP(K)
Printed in Japan
The mark Ì shows major revised points.
2002

1 Page





UPD44323362 pdf, ピン配列
µPD44323362
Pin Name and Functions
Pin name
Description
Function
VDD
VSS
VDDQ
VREF
K, /K
Core Power Supply
Ground
Output Power Supply
Input Reference
Main Clock
Supplies power for RAM core
Supplies power for output buffers
SA0 to SA19
Synchronous Address Input
DQa1 to DQd9 Synchronous Data Input / Output
/SS Synchronous Chip Select
Logically selects SRAM
/SW
Synchronous Byte Write Enable
Write command
/SBa
Synchronous Byte "a" Write Enable
Write DQa1 to DQa9
/SBb
Synchronous Byte "b" Write Enable
Write DQb1 to DQb9
/SBc
Synchronous Byte "c" Write Enable
Write DQc1 to DQc9
/SBd
Synchronous Byte "d" Write Enable
Write DQd1 to DQd9
/G Asynchronous Output Enable Asynchronous input
ZZ Asynchronous Sleep Mode
Enables sleep mode, active high
ZQ
M1, M2
Output Impedance Control
Mode Select
Selects operation mode Note
NC No Connection
TMS
Test Mode Select (JTAG)
TDI Test Data Input (JTAG)
TCK
Test Clock Input (JTAG)
TDO
Test Data Output (JTAG)
Note This device only supports Single Differential Clock, R/R Mode.
(R/R stands for Registered Input / Registered Output.)
Data Sheet M16379EJ4V0DS
3


3Pages


UPD44323362 電子部品, 半導体
µPD44323362
Synchronous Truth Table
ZZ /SS /SW /SBa /SBb /SBc /SBd Mode DQa1 to DQa9 DQb1 to DQb9 DQc1 to DQc9 DQd1 to DQd9 Power
L H × × × × × Not selected High-Z
High-Z
High-Z
High-Z
Active
L LH× × × ×
Read
Dout
Dout
Dout
Dout
Active
LLLLLLL
Write
Din
Din
Din
Din Active
L L L LHHH
Write
Din
High-Z
High-Z
High-Z
Active
L L LHL L L
Write
High-Z
Din
Din
Din Active
H × × × × × × Sleep Mode
High-Z
High-Z
High-Z
High-Z Standby
Remark × : Don't care
Output Enable Truth Table
Mode
Read
Read
Sleep (ZZ = H)
Write (/SW = L)
Deselect (/SS = H)
/G
L
H
×
×
×
DQ
Dout
High-Z
High-Z
High-Z
High-Z
Mode Select (I/O) Note 1
M1 M2
Mode
VSS VDD Single Differential Clock (K, /K), R/R Mode Note 2
Notes
1. This device only supports Single Differential Clock, R/R Mode. Mode Select Pins (M1, M2) are to be tied
to either VDD or VSS.
2. R/R: Registered Input / Registered Output
Mode Select (Output Buffer)
ZQ Mode
IZQ × RQ
VDD
Controlled impedance push-pull output buffer mode
Push-pull output buffer mode
Notes 1. See figure.
ZQ
Note
1
2
2. See figure.
VDD
ZQ
6
Data Sheet M16379EJ4V0DS

6 Page



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部品番号部品説明メーカ
UPD44323362

32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM

NEC
NEC


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