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ADV202 の電気的特性と機能

ADV202のメーカーはAnalog Devicesです、この部品の機能は「Video Codec」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADV202
部品説明 Video Codec
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADV202 Datasheet, ADV202 PDF,ピン配置, 機能
Data Sheet
FEATURES
Complete single-chip JPEG2000 compression and
decompression solution for video and still images
Patented SURF® (spatial ultra-efficient recursive filtering)
technology enables low power and low cost wavelet-
based compression
Supports both 9/7 and 5/3 wavelet transforms with up to
6 levels of transform
Programmable tile/image size with widths up to 2048 pixels in
3-component 4:2:2 interleaved mode, and up to 4096 pixels
in single-component mode
Maximum tile/image width: 4096 pixels
Video interface directly supporting ITU.R-BT656,
SMPTE125M PAL/ NTSC, SMPTE274M, SMPTE293M (525p),
ITU.R-BT1358 (625p) or any video format with a maximum
input rate of 65 MSPS for irreversible mode or 40 MSPS for
reversible mode
Two or more ADV202s can be combined to support full-
frame SMPTE274M HDTV (1080i) or SMPTE296M (720p)
Flexible asynchronous SRAM-style host interface allows
glueless connection to most 16-/32-bit microcontrollers
and ASICs
2.5 V to 3.3 V I/O and 1.5 V core supply
12 mm × 12 mm 121-lead CSPBGA, speed grade 115 MHz, or
13 mm × 13 mm 144-lead CSPBGA, speed grade 135 MHz, or
13 mm × 13 mm 144-lead CSPBGA, speed grade 150 MHz
JPEG2000 Video Codec
ADV202
APPLICATIONS
Networked video and image distribution systems
Wireless video and image distribution
Image archival/retrieval
Digital CCTV and surveillance systems
Digital cinema systems
Professional video editing and recording
Digital still cameras
Digital camcorders
GENERAL DESCRIPTION
The ADV202 is a single-chip JPEG2000 codec targeted for
video and high bandwidth image compression applications that
can benefit from the enhanced quality and feature set provided
by the JPEG2000 (J2K)—ISO/IEC15444-1 image compression
standard. The part implements the computationally intensive
operations of the JPEG2000 image compression standard as well
as providing fully compliant code-stream generation for most
applications.
The ADV202’s dedicated video port provides glueless connection
to common digital video standards such as ITU.R-BT656,
SMPTE125M, SMPTE293M (525p), ITU.R-BT1358 (625p),
SMPTE274M (1080i), or SMPTE296M (720p). A variety of other
high speed, synchronous pixel and video formats can also be sup-
ported using the programmable framing and validation signals.
(continued on Page 4)
PIXEL I/F
HOST I/F
FUNCTIONAL BLOCK DIAGRAM
PIXEL I/F
EXTERNAL
DMA CTRL
ADV202
WAVELET
ENGINE
EC1
EC2 EC3
PIXEL FIFO
CODE FIFO
ATTR FIFO
INTERNAL BUS AND DMA ENGINE
EMBEDDED
RISC
PROCESSOR
SYSTEM
RAM
ROM
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.

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ADV202 pdf, ピン配列
ADV202
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
JPEG2000 Feature Support.......................................................... 4
Specifications..................................................................................... 5
Supply Voltages and Current ...................................................... 5
Input/Output Specifications........................................................ 5
Clock and RESET Specifications ................................................ 6
Normal Host Mode—Read Operation ...................................... 7
Normal Host Mode—Write Operation ..................................... 8
DREQ/DACK DMA Mode—Single FIFO Write Operation .. 9
DREQ/DACK DMA Mode—Single FIFO Read Operation . 11
External DMA Mode—FIFO Write, Burst Mode .................. 13
External DMA Mode—FIFO Read, Burst Mode ................... 14
Streaming Mode (JDATA)—FIFO Read/Write ...................... 16
VDATA Mode Timing ............................................................... 17
Raw Pixel Mode Timing ............................................................ 18
Absolute Maximum Ratings.......................................................... 19
Thermal Resistance .................................................................... 19
ESD Caution................................................................................ 19
Pin BGA Assignments and Function Descriptions ................... 20
Pin BGA Assignments ............................................................... 20
Pin Function Descriptions ........................................................ 23
Theory of Operation ...................................................................... 26
Wavelet Engine ........................................................................... 26
Entropy Codecs........................................................................... 26
Data Sheet
Embedded Processor System .................................................... 26
Memory System.......................................................................... 26
Internal DMA Engine ................................................................ 26
ADV202 Interface........................................................................... 27
Video Interface (VDATA Bus).................................................. 27
Host Interface (HDATA Bus) ................................................... 27
Direct and Indirect Registers.................................................... 27
Control Access Registers ........................................................... 27
Pin Configuration and Bus Sizes/Modes ................................ 28
Stage Register .............................................................................. 28
JDATA Mode............................................................................... 28
External DMA Engine ............................................................... 28
Internal Registers............................................................................ 29
Direct Registers........................................................................... 29
Indirect Registers........................................................................ 30
PLL ............................................................................................... 31
Hardware Boot............................................................................ 31
Video Input Formats ...................................................................... 32
Applications..................................................................................... 34
Encode—Multichip Mode......................................................... 34
Decode—Multichip Master/Slave ............................................ 35
Digital Still Camera/Camcorder .............................................. 35
Encode/Decode SDTV Video Application ............................. 36
ASIC Application (32-Bit Host/32-Bit ASIC)......................... 37
HIPI (Host Interface—Pixel Interface) ................................... 38
JDATA Interface ......................................................................... 38
Outline Dimensions ....................................................................... 39
Ordering Guide .......................................................................... 40
Rev. D | Page 2 of 40


3Pages


ADV202 電子部品, 半導体
Data Sheet
ADV202
SPECIFICATIONS
SUPPLY VOLTAGES AND CURRENT
Table 1.
Parameter
VDD
IOVDD
PLLVDD
VINPUT
Temp
IDD
Description
DC Supply Voltage, Core
DC Supply Voltage, I/O
DC Supply Voltage, PLL
Input Range
Operating Ambient Temperature Range in Free Air
Static Current1
Dynamic Current, Core (JCLK Frequency = 150 MHz)2
Dynamic Current, Core (JCLK Frequency = 108 MHz)
Dynamic Current, Core (JCLK Frequency = 81 MHz)
Dynamic Current, I/O
Dynamic Current, PLL
1 No clock or I/O activity.
2 ADV202-150 only.
Min
1.425
2.375
1.425
−0.3
−40
INPUT/OUTPUT SPECIFICATIONS
Table 2.
Parameter
VIH (3.3 V)
VIH (2.5 V)
VIL (3.3 V, 2.5 V)
VOH (3.3 V)
VOH (2.5 V)
VOL (3.3 V, 2.5 V)
IIH
IIL
IOZH
IOZL
CI
CO
Description
High Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
High Level Three-State Leakage Current
Low Level Three-State Leakage Current
Input Pin Capacitance
Output Pin Capacitance
Test Conditions
VDD = max
VDD = max
VDD = min
VDD = min, IOH = −0.5 mA
VDD = min, IOH = −0.5 mA
VDD = min, IOL = 2 mA
VDD = max, VIN = VDD
VDD = max, VIN = 0 V
VDD = max, VIN = VDD
VDD = max, VIN = 0 V
Typ Max
1.5 1.575
3.3 3.63
1.5 1.575
VDDI/O + 0.3
+25 +85
300
570
420
325
20
2.6
Unit
V
V
V
V
°C
mA
mA
mA
mA
mA
mA
Min Typ Max Unit
2.2 V
1.9 V
0.6 V
2.4 V
2.0 V
0.4 V
1.0 µA
1 µA
1.0 µA
1.0 µA
8 pF
8 pF
Rev. D | Page 5 of 40

6 Page



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部品番号部品説明メーカ
ADV202

Video Codec

Analog Devices
Analog Devices


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