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PDF ISL55141 Data sheet ( Hoja de datos )
| Número de pieza | ISL55141 | |
| Descripción | (ISL55141 - ISL55143) High Speed 18V CMOS Comparators | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
High-Speed 18V CMOS Comparators
ISL55141, ISL55142, ISL55143 integrated circuits are
high-speed, wide input common-mode range comparators.
They provide three-state window comparators in a high
voltage CMOS process (18V). Each comparator has dual
receive thresholds, CVA and CVB, for establishing
minimum 1-VIH and maximum 0-VIL voltage levels. These
devices can accept inputs from a number of logic families,
such as TTL, ECL, CMOS, LVCMOS, LVDS and CML. Two
bits of output per comparator provide the test controller with
qualification of a comparator input into three states. The two
output bits work with a separate user supply to establish
VOH, VOL levels compatibility with the system’s controller
logic levels.
Fast propagation delay (9.5ns typical at ±50mV overdrive)
makes this family compatible with high-speed digital test
systems. The 18V range enables the comparator input to
operate over a wide input range. Two references per input
enable and three state digitization of input with voltage
swings of up to 13V common mode. The operating
frequency of these devices is typically 65MHz.
High voltage CMOS process makes these devices ideal for
large voltage swing applications, such as special test
voltages levels associated with Flash devices or power
supervision applications and may avoid the need for test bus
isolation relay(s).
Functional Block Diagram
DUAL LEVEL COMPARATOR - RECEIVERS
VOH
QAX
VOL
VOH
QBX
VOL
VCC
VEE
VCC
VEE
CVAX
VINPX
CVBX
x denotes 1, 2 or 4 channels for ISL55141, ISL55142 and ISL55143,
respectively
ISL55141, ISL55142, ISL55143
July 17, 2006
FN6230.0
Features
• 18V I/O range
• 65MHz operation
• 9.5ns typical propagation delay
• Programmable input thresholds
• User defined comparator output levels
• Common-mode range includes negative rails
• Small footprints in QFN packages
• Power-down current <10µA
• Pb-free plus anneal available (RoHS compliant)
Applications
• Burn in ATE
• Low cost ATE
• Fast supervisory power control
• Instrumentation
Ordering Information
PART
PART
TEMP.
PKG.
NUMBER MARKING RANGE (°C) PACKAGE DWG. #
ISL55141IRZ* 55141IRZ -40 to +85 16 Ld QFN L16.4X4A
(See Note)
(Pb-free)
ISL55141IVZ* 55141IVZ -40 to +85 14 Ld TSSOP M14.173
(See Note)
(Pb-free)
ISL55142IRZ* 55142IRZ -40 to +85 20 Ld QFN L20.5x5
(See Note)
(Pb-free)
ISL55142IVZ* 55142IVZ -40 to +85 20 Ld TSSOP M20.173
(See Note)
(Pb-free)
ISL55143IRZ* 55143IRZ -40 to +85 36 Ld TQFN L36.6X6
(See Note)
(Pb-free)
* Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
DataSheet4 U .com
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
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ISL55141, ISL55142, ISL55143
Electrical Specifications Test Conditions: VCC = 12V, VEE = -3V, VOH = 5V, VOL = 0V, PD = VEE, CLOAD = 15pF, TA = 25°C, unless
otherwise specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
UNITS
DIGITAL OUTPUTS QAX, QBX
Output Resistance
RoutR
18 27 37
Ω
Output Logic High Voltage
VOH
Output Logic Low Voltage
VOL
POWER SUPPLIES, STATIC CONDITIONS
VOH = 5V, ISOURCE = 1mA
VOL = 0V, ISINK = 1mA
4.9 4.95
0.00 0.05
5.0
0.1
V
V
Positive Supply DC Current/Comparator ICC No input data
Negative Supply Current/Comparator
Total Power Dissipation/Comparator
IEE No input data
P† Input data at 40MHz
-12.5
+8.25
-8.25
670
12.5
mA
mA
mW
†Total Power dissipation per comparator can be approximately calculated from the following:
P = (VCC-VEE)*8.25mW + 90pF*(VCC-VEE)^2*f + CL*(VCC-VEE)^2*f
where f is the operating frequency and CL is the load capacitance.
Because the ISL55142 has two comparators, the power dissipation would be twice of P calculated from the above equation. The ISL55143 would
be four times P.
NOTES:
3. Lab characterization, room temperature, timing parameters matched stimulus/loads, channel-to-channel skew < 500ps, 1ns maximum by design
4. Note about ICC measurement input can approach 140mA (single comparator) at maximum pattern rates
5. Not 100% Tested
Test Circuits and Waveforms
DATA = 1
DATA = 0 400mV
VINPX
tPDLH
QAX, QBX
50%
tR
0V
tPDHL
50%
VOH (≈VH)
VOL (≈VL)
tF
FIGURE 1. COMPARATOR PROPAGATION DELAY AND TRANSITION TIME MEASUREMENT POINTS
CVA 2.4V
VINP
CVB 0.4V
+
- VCC
+ VEE
-
Although there is no electrical difference between the CVA
and CVB Inputs, if one defines CVA as being the high
threshold and CVB being the low threshold, it becomes
easier to understand the utilization of a dual threshold
comparator. Essentially this enables the qualification of an
QA incoming signal into three states. In the case pictured, the
three states are Valid Low <0.4V, No-man’s-land (between
0.4 and 2.4V), Valid High >2.4V. Table 2 shows how the
QA/QB truth table would be utilized in the real world.
QB TABLE 2. QA/QB TRUTH TABLE
<0.4V
VINP
QA QB COMMENT
0 0 Valid 0
>0.4 and <2.4V
0 1 Invalid
>2.4V
1 1 Valid 1
FIGURE 2. THREE-STATE WINDOW COMPARATOR FUNDAMENTALS
DataSheet4 U .com
5
FN6230.0
July 17, 2006
5 Page 
www.DataSheet4U.com
ISL55141, ISL55142, ISL55143
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX
AREA
E1
-B-
E
0.25(0.010) M B M
GAUGE
PLANE
123
0.05(0.002) SEATING PLANE
-A- D
A
0.25
0.010
L
-C-
e A1
b
0.10(0.004) M C A M B S
α
A2
0.10(0.004)
c
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15
-
A2 0.031 0.041 0.80 1.05
-
b
0.0075 0.0118 0.19
0.30
9
c
0.0035 0.0079 0.09
0.20
-
D 0.195 0.199 4.95 5.05
3
E1 0.169 0.177 4.30 4.50
4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50
-
L
0.0177 0.0295 0.45
0.75
6
N 14
14 7
α
0o 8o 0o 8o
-
Rev. 2 4/06
DataSheet4 U .com
11
FN6230.0
July 17, 2006
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ISL55141.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL55141 | (ISL55141 - ISL55143) High Speed 18V CMOS Comparators | Intersil Corporation |
| ISL55142 | (ISL55141 - ISL55143) High Speed 18V CMOS Comparators | Intersil Corporation |
| ISL55143 | (ISL55141 - ISL55143) High Speed 18V CMOS Comparators | Intersil Corporation |
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