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ISL5586 の電気的特性と機能

ISL5586のメーカーはIntersil Corporationです、この部品の機能は「Low Power Ringing SLIC」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL5586
部品説明 Low Power Ringing SLIC
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL5586 Datasheet, ISL5586 PDF,ピン配置, 機能
www.DataSheet4U.com
TM
Data Sheet
ISL5586
June 2001
File Number 4924.1
Low Power Ringing SLIC for Home
Gateways
The ISL5586 is a very low
power Ringing Subscriber
Interface circuit designed for
use with the Broadcom*
BCM3352 Cable Modem
Chip, with on-board voiceband codecs, or other 3.3V
voiceband codec devices.
The ISL5586 provides on board ringing signal generation up
to 95V peak supporting sinusoidal or trapezoidal
waveshapes with DC offset. Loop start and ground start
trunks are supported, and an open circuit DC voltage of less
than 56V is maintained on the subscriber loop in the on-hook
condition, in compliance with MTU operation and the safety
requirements of UL-1950.
Together with the Broadcom BCM3352, the ISL5586
provides resistive and complex two wire impedance
matching and transhybrid balancing. Also supported are on-
hook transmission of caller id signals, soft and hard polarity
reversal and 12/16kHz subscriber pulse metering systems
used in Europe and Asia, thereby allowing a low cost, low
risk, global product design to be achieved.
Related Literature
• Evaluation Board for the ISL5586 family AN9918
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Block Diagram
POL CDCP CDCM
VBL VBH
ILIM
DC
CONTROL
BATTERY
SWITCH
TIP
RING
TL
2-WIRE
PORT
TRANSIENT
CURRENT
LIMIT
TRANSMIT
SENSING
INTERNAL
LOOP BACK
DETECTOR
LOGIC
RTD RD
*Broadcom is a registered trademark of Broadcom Corp.
DET
Features
• Interfaces to Broadcom 3352 cable modem device
• Very low on-hook power consumption
- 64mW @ Vbh = 75V
• User Programmable constant current to the subscriber
loop
• On Chip ring generation
- Balanced to 95 Vpk
• Sinewave, Trapezoid, DC offset
• Programmable loop start and ring trip detectors
• Loop start, Ground Start, Polarity Reversal (soft/hard)
• On-Hook transmission and pulse metering support
• Integrated battery switch
• Open circuit line voltage clamp
• Compatible with 3.3V devices
• TR-57 compliant Longitudinal balance
• 28 PLCC packaging
• Latch-up free Bipolar design
• Thermal protection
Applications
• Cable Modems
• Voice Over DSL (VoDSL)
• Broadband Wireless Access
• Voice Over Internet Protocol (VoIP)
• ISDN Terminal Adapters (TA)
• Small Office Home Office PBX
• Wireless Local Loop
RINGING
PORT
4-WIRE
PORT
CONTROL
LOGIC
BSEL
VRSP
VRSM
VRXP
VRXM
-IN
VZO
VFB
VTXP
VTXM
F2
F1
F0
4-1
RSLIC18™ is a trademark of Intersil Corporation.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved

1 Page





ISL5586 pdf, ピン配列
ISL5586
Absolute Maximum Ratings TA = 25oC
Maximum Supply Voltages
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
VCC - VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110V
ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Maximum Tip/Ring Negative Voltage Pulse (Note 7) . . . . . .VBH-15V
Maximum Tip/Ring Positive Voltage Pulse (Note 7). . . . . . . . . . + 8V
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(PLCC - Lead Tips Only)
Operating Conditions
Temperature Range
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Positive Power Supply (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V
Negative Power Supply (VBH, VBL). . . . . . . . . . . . . . -100V to -24V
Die Characteristics
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VBH
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V,
AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600,
2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection
resistors = 0. These parameters apply generically to each product offering.
PARAMETER
TEST CONDITIONS
RINGING PARAMETERS
VRSP Input Impedance (Note 2)
VRSM input impedance (Note 2)
Differential Ringing Gain (Note 3)
Ringing voltage Total Distortion
4-Wire to 2-Wire Ringing Off Isolation
2-Wire to 4-Wire Transmit Isolation
VRS to 2-Wire, RLOAD = 5 REN
RL = 1.3 k, VT-R = |VBH| -5
Forward Active Mode, Referenced to VRS Input.
Ringing Mode Referenced to the Differential
Ringing Amplitude.
Centering Voltage Accuracy
AC TRANSMISSION PARAMETERS
Tip, Referenced to VBH/2 + 0.5V
Ring, Referenced to VBH/2 + 0.5V
Receive Input Impedance, VRXP (Note 2)
Receive input Impedance, VRXM (Note 2)
Transmit Output Impedance (Note 2)
DC
Transmit Output Drive Capability (Note 2)
Current
Capacitance to Ground
4-Wire Port Overload Level
THD = 1%
2-Wire Port Overload Level
THD = 1%
2-Wire Return Loss (Note 2)
200Hz f 1kHz
1kHz f 3.4kHz
Longitudinal Current Capability per Wire (Note 2)
False Detect
False Detect in Low Power Standby
2-Wire Longitudinal Balance (ON-Hook and OFF-Hook) 200Hz, 500Hz, 1000Hz
(Notes 4, 5)
3000Hz
4-Wire Longitudinal Balance (ON-Hook and OFF-Hook) 200Hz, 500Hz, 1000Hz
(Notes 4, 5)
3000Hz
4-Wire to 2-Wire Insertion Loss
0dBmo at 1kHz
2-Wire to 4-Wire Insertion Loss
0dBmo at 1kHz
4-Wire to 4-Wire Insertion Loss
0dBmo at 1kHz
Frequency Response, On Hook, 2-Wire to 4-Wire, 4-Wire Referenced to 0dBmo at 1004Hz,
to 2-Wire, 4-Wire to 4-Wire
400Hz f 2800Hz
Frequency Response, Off Hook
2-Wire to 4-Wire, 4-Wire to 2-Wire, 4-Wire to 4-Wire
Referenced to 0dBmo at 1004Hz, f = 400Hz,
2800Hz
MIN TYP
35 -
10 -
- 99.5
- 0.8
- 100
- 100
-3.0 0.2
-3.0 0.2
379
100
-
0.30
-
3.1
3.1
-
-
20
10
58
53
58
53
2.72
-0.2
2.72
-0.15
541
142
0.01
1.0
1.0
3.5
3.5
35
23
-
-
61
61
64
62
2.92
0
2.92
0.03
-0.15 0.03
MAX UNITS
- M
- M
- V/V
5%
- dB
- dB
3.0 V
3.0 V
-
-
-
-
100
-
-
-
-
-
-
-
-
-
-
3.12
0.2
3.12
0.15
k
k
mA
pF
VPEAK
VPEAK
dB
dB
mARMS
mARMS
dB
dB
dB
dB
dB
dB
dB
dB
.15 dB
4-3


3Pages


ISL5586 電子部品, 半導体
ISL5586
Electrical Specifications
Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V,
AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600,
2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection
resistors = 0. These parameters apply generically to each product offering. (Continued)
PARAMETER
VBH to 4-Wire, BSEL = 2.0V
NOTES:
TEST CONDITIONS
f = 50Hz
f = 300Hz f 3400Hz
f = 8kHz f 16kHz
MIN TYP MAX UNITS
- 76 -
dB
- 55 -
dB
- 42 -
dB
2. These parameters are controlled via design and Statistical Process Control and are not directly tested. These parameters are characterized upon
initial design release and upon design changes which would affect these characteristics.
3. Input voltage = 0.636VRMS for VBH = -100V, 0.530VRMS for VBH = -85V and 0.460VRMS for -75V devices.
4. Tested per IEEE455-1985, with 368resistors connected to the Tip and Ring terminals.
5. These parameters are tested 100% at room temperature, and are guaranteed but not tested across the full temperature range via statistical
characterization and design.
6. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current limits.
7. Characterized with 2 x 10us and 10 x 1000us first level lightning surge waveform (GR-1089-CORE).
Design Equations
Refer to Figure 14 for programming resistor connections.
Loop Supervision Thresholds
SWITCH HOOK DETECT
The desired switch hook detect threshold current (ISH) is set by
a single external resistor, RSH as follows
RSH = 615 ISH
(EQ. 1)
The loop current threshold programming range is from 5mA
to 15mA.
RING TRIP DETECT
The ring trip detect threshold (IRT) is set by a single external
resistor, RRT as follows.
RRT = 1800 IRT
(EQ. 2)
IRT should be set between the peak ringing current and the
peak off hook current while still ringing. In addition, the ring
trip current must be set below the transient current limit
including tolerances. The ringing signal filter capacitor CRT,
in parallel with RRT sets the ring trip response time.
LOOP CURRENT LIMIT
The DC loop current limit (ILIM) is programmed by the
external resistor RIL as follows.
RIL = 1-I--L-7---I6--M--0-
(EQ. 3)
The loop current limit programming range is from 15mA to
45mA.
Impedance Matching
The AC source impedance of the SLIC is programmed with
the external impedance network ZS as described next. To
synthesize and match Resistive line terminations the
programming network is simply a resistor (RS) as shown in
Figure 14. For complex line terminations such as the one
illustrated in Figure 1, a complex programming network is
required.
RESISTIVE IMPEDANCE SYNTHESIS
The AC source resistance of the SLIC is synthesized with a
single external resistor RS as follows:
RS
=
Z0
×
4----03---0--
=
133.3 ( Z0 )
(EQ. 4)
The synthesized resistance (Z0) is determined by the
characteristic line resistance and protection resistors as
shown in Equation 5.
ZO = RL (RP1 + RP2)
(EQ. 5)
COMPLEX IMPEDANCE SYNTHESIS
A complex network is used in place of RS when the termination
impedance of the line is complex as shown in Figure 1.
2-WIRE TERMINATION
IMPEDANCE (ZL)
C2
R1
R2
PROGRAMMING
NETWORK (ZS)
CP
RS
RP
FIGURE 1. COMPLEX PROGRAMMING NETWORK
The component RS has a different design equation than the
RS used for resistive impedance synthesis. The design
equations for each component are provided below where
RP1 and RP2 are the protection resistors and RP is a
component of the programming network.
RS = 133.3 × (R1 RP1 RP2)
RP = 133.3 × R2
CP = C2 133.3
(EQ. 6)
(EQ. 7)
(EQ. 8)
4-6

6 Page



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