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PDF ISL55100A Data sheet ( Hoja de datos )

Número de pieza ISL55100A
Descripción Quad 18V Pin Electronics Driver/Window Comparator
Fabricantes Intersil Corporation　
Logotipo Intersil Corporation Logotipo



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No Preview Available ! ISL55100A Hoja de datos, Descripción, Manual

DATASHEET
Quad 18V Pin Electronics Driver/Window Comparator
ISL55100A
The ISL55100A is a Quad pin driver and window comparator
fabricated in a wide voltage CMOS process. It is designed
specifically for Test During Burn In (TDBI) applications, where
cost, functional density and power are all at a premium.
This IC incorporates four channels of programmable drivers
and window comparators into a small 72 Ld QFN package.
Each channel has independent driver levels, data and high
impedance control. Each receiver has dual comparators, which
provide high and low threshold levels.
The ISL55100A uses differential mode digital inputs and can
therefore mate directly with LVDS or CML outputs.
Single-ended logic families are handled by connecting one of
the digital input pins to an appropriate threshold voltage (e.g.,
1.4V for TTL compatibility). The comparator outputs are
single-ended and the output levels are user defined to mate
directly with any digital technology.
The 18V driver output and receiver input ranges allow this
device to interface directly with TTL, ECL, CMOS (3V, 5V and
7V), LVCMOS and custom level circuitry, as well as the high
voltage (super voltage) level required for many special test
modes for Flash Devices.
Features
• Low driver output resistance
- ROUT maximum: ISL55100A 7.0Ω
• 18V I/O range
• 50MHz operation
• 4-channel driver/receiver pairs with per pin flexibility
• Dual level - per pin - input thresholds
• Differential or single-ended digital inputs
• User defined comparator output levels
• Low channel-to-channel timing skew
• Small footprint (72 Ld QFN)
• Pb-free (RoHS compliant)
Applications
• Burn in ATE
• Wafer level flash memory test
• LCD panel test
• Low cost ATE
• Instrumentation
• Emulation
• Device programmers
Functional Block Diagram
QUAD - WIDE RANGE, LOW ROUT, TRI-STATEABLE - DRIVERS
DATA+(0:3)
DATA-(0:3)
DRVEN+(0:3)
DRVEN-(0:3)
+
-
+
-
VH(0:3)
DOUT(0:3)
VL(0:3)
QUAD - DUAL LEVEL COMPARATOR - RECEIVERS
COMP HIGH
QA(0:3)
COMP LOW
COMP HIGH
QB(0:3)
COMP LOW
VCC
+
-
VEE
VCC
+
-
VEE
CVA(0:3)
VINP(0:3)
CVB(0:3)
December 4, 2014
FN7486.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2008, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 page




ISL55100A pdf
ISL55100A
Electrical Specifications
PARAMETER
Test Conditions: VCC = 12V, VEE = -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp-Low = 0V, V5V = VEE and
LOWSWING = VCC. (Continued)
SYMBOL
TEST CONDITIONS
MIN TYP MAX
UNITS
Enable Time
tEN DVRENTransition from Disable to Enable:
13
15
23
Lowswing Disabled (Note 9)
ns
DVRENTransition from Disable to Enable:
13
18
23
Lowswing Enabled (Note 9)
ns
ISL55100A Rise/Fall Times (Note 7)
tR, tF
100pF Load
V = 0.4V (20% to 80%)
V = 1V (20% to 80%)
-
-
2.5
2.5
-
-
ns
ns
V = 5V (10% to 90%)
- 2.5
-
ns
V = 10V (10% to 90%)
- 2.5
-
ns
V = 14V (10% to 90%)
- 2.5
-
ns
ISL55100A Rise/Fall Times (Note 7)
tR, tF
1000pF Load
V = 1V (20% to 80%)
V = 5V (10% to 90%)
- 8.0
- 10.0
-
-
ns
ns
V = 10V (10% to 90%)
- 14.0
-
ns
ISL55100A Maximum Toggle Frequency FMAXD No Load, 50% Symmetry
50 65
-
MHz
ISL55100A Min Driver Pulse Width
ISL55100A Overshoot Lowswing Mode
(Note 7)
tWIDD
OS
Standard Load, 1k/100pF (Note 8)
Lowswing Enabled, (VH - VL < 2V)
- 7.7
- 20mV+
10% of
output
swing
-
ns
%V
RECEIVER DC CHARACTERISTICS
Input Offset Voltage
Input Bias Current
Output Resistance
RECEIVER TIMING CHARACTERISTICS
VOS
IBIAS
ROUTR
CVA = CVB = 1.5V
VINP - CV(A/B) = ±5V
-50 -
- 10
18 25
50
30
35
mV
nA
Ω
Propagation Delay
Maximum Operating Frequency
Minimum Pulse Width
Rcvr Channel-to-channel Skew (Note 7)
tPP
FMAXR
tWIDR
Under No Load, PWOUT Symmetry 50%
7 12
50 65
- 7.7
- <1
18
-
-
-
ns
MHz
ns
ns
DIGITAL INPUTS
Differential Input High Voltage
VDIFFH VDIG+ - VDIG-
200 -
-
Differential Input Low Voltage
VDIFFL VDIG+ - VDIG-
- - -200
Input Current
IIN VIN = VCC or VEE
-50 0
50
Common Mode Input Voltage Range
VCM VDIFFL > VDIFFH - 0.2V
VCC - 5V
VDIFFH < VDIFFL + 0.2V
VEE + 0.2V
-
-
POWER SUPPLIES, DRIVER/RECEIVER STATIC CONDITIONS VEXT = VEE, EXTERNAL LOGIC POWER OPTION NOT USED. (Notes 10, 11)
Positive Supply Current
ICC VCC = VH = 12V, VEE = VL = -3V, VEXT = VEE,
Outputs Unloaded
-
65 85
mV
mV
nA
V
V
mA
Negative Supply Current
IEE VCC = VH = 12V, VEE = VL = -3V, VEXT = VEE, -85
Outputs Unloaded
-65
-
mA
VEXT Supply Current
IEXT VCC = VH = 12, VEE = VL = -3V, VEXT = VEE,
Outputs Unloaded
-
<1
-
mA
POWER SUPPLIES, DRIVER/RECEIVER STATIC CONDITIONS VEXT = VEE + 5.5V, EXTERNAL LOGIC POWER OPTION USED. (Notes 11, 12)
Positive Supply Current
ICC VCC = VH = 12V, VEE = VL = -3V, VEXT = VEE
+ 5.5V, Outputs Unloaded
-
35 50
mA
Submit Document Feedback
5
FN7486.3
December 4, 2014

5 Page





ISL55100A arduino
ISL55100A
Typical Performance Curves Device installed on Intersil ISL55100A Evaluation Board.
VVCECE
12.0
- 3.0
VH
VL
2.0
0.0
LOWSWING OFF
0
LOWSWING ON
0
10ns/DIV
FIGURE 7. LOWSWING EFFECTS ON DRIVER SHAPE AND tPD
(100pF-1k LOAD)
0 DATA IN
VVCECE
12.0
- 3.0
VH
VL
6.0
0.0
1k/100pF
680pF
2200pF
0 1000pF
10ns/DIV
FIGURE 8. DRIVER WAVEFORMS UNDER VARIOUS LOADS
DRVEN
0
DATA IN
0
0
VVCECE
12.0
- 3.0
VH
VL
6.0
0.0
DRIVER OUT
20ns/DIV
FIGURE 9. DATA/HIZ/DRIVER OUT TIMING
6
VH (6.00V) ROUT: DRIVER SOURCES 200mA
5
4
3 VL (0.0V) ROUT: DRIVER SINKS 200mA
2
1
0 12 13 14 15 16 17
VCC - VEE VOLTS (VEE - 3.0 FIXED)
FIGURE 10. ROUT vs DEVICE VOLTAGE
18
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0 1
VH (1V-15V) ROUT: DRIVER SOURCES 200mA
VL (0.0V FIXED) ROUT: DRIVER SINKS 200mA
2 3 4 5 6 7 8 9 10 11 12 13 14 15
VH VOLTS (VL = 0.0)
FIGURE 11. ROUT vs VH RAIL
20
18
16 2200pF
14 1000pF
12 680pF
10
1k/100pF
8
6
4
2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
VH VOLTS (VL = 0.0)
FIGURE 12. PROPAGATION DELAY vs VH RAIL, VARIOUS LOADS
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December 4, 2014

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