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PDF AN-136 Data sheet ( Hoja de datos )
| Número de pieza | AN-136 | |
| Descripción | A NEW GENERATION | |
| Fabricantes | Integrated Device Technology | |
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Integrated Device Technology, Inc.
A NEW GENERATION OF
TAG SRAMS—THE IDT71215 AND
IDT71216
By Kelly Maas
APPLICATION
NOTE
AN-136
INTRODUCTION
The 71215 and 71216 represent a new generation of
integrated Tag SRAMs. Just as earlier Tag SRAMs such as
the 71B74 were better suited for tag applications than conven-
tional SRAMs, the 71215/16 go a step further by integrating
new features to significantly ease the design of high perfor-
mance cache subsystems for today’s high speed processors.
These Tag RAMs are designed for easy interfacing to Intel and
PowerPC processors, but are very flexible and can easily be
used in other applications as well.
This application note first provides some background infor-
mation on caches, then describes in detail the architecture
and operation of the 71215 and 71216. This is followed by
three application examples, then a brief discussion of cache
coherency protocol implementation using these Tag RAMs.
Since the 71215 and 71216 are very similar, the descriptions
and explanations in this application note apply to both unless
otherwise noted.
CACHE AND TAG BASICS
For those new to caches, a brief review of cache basics may
be worthwhile. A cache is a memory that provides a CPU with
high speed access to a subset of the data from main memory.
Our discussions are focused on the secondary cache, which
is also known as the L2 cache, but it is not much different from
the faster primary (L1) cache residing inside most CPUs.
The cache consists of a controller, a data memory and a tag
memory. The purpose of the data memory is to store the
active data from main memory, and is composed of either
synchronous burst or asynchronous SRAMs. The tag memory
stores indexes (part of the CPU address field) that indicate
which data is stored in the cache. Additionally, most caches
also require at least one bit of memory for each cache entry,
to indicate the valid or dirty status of that entry. Figure 1 shows
how the CPU address field relates to the cache and the tag
memory. This example includes valid and dirty status bits, and
represents a 512KB cache, 2GB cacheable address space,
32-byte line size, and 8-byte word size.
A31
MSB
A30
A19 A18
TAG MEMORY
12 1
1
TAG
LINE
VALID
LINE
DIRTY
DATA SRAM ADDRESS
A5 A4
A3
LSB
TAG
ADDRESS
COMPARATOR
MATCH
to CACHE CONTROLLER
3176 drw 01
Figure 1. CPU Address Field and the L2 Cache (Showing 512 KB cache size and 2 GB cacheable main memory)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
PowerPC is a trademark of International Business Machines Corporation
Pentium is a trademark of Intel Corporation
©1995 Integrated Device Technology, Inc.
1/95
1 page  
A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216
APPLICATION NOTE AN-136
The 71215/16 is shown in more detail in Figure 4. The tag
memory is controlled by the Write Enable Tag (WET ) and
Output Enable Tag (OET ) pins. During writes, WET is synchro-
nous to CLK, as are the input data (TAG0 - TAG11) and
address (A0 - A13). Note that WET has no effect on the TAG
output buffers, so OET must be high to disable the outputs
during writes. Reads are performed by deasserting WET and
asynchronously asserting OET . For cache architectures in
which the tag is never read (e.g. write-through caches), OET
may be tied to VCC. When both WET and OET are high, the
71215/16 is in the match mode, where the TAG0 - TAG11
inputs are compared with the stored data and are used to
generate the MATCH and BRDY /TA outputs. In both read and
match modes, the address path is flow-through for the fastest
possible response to a new address.
The three status bits of the 71215/16 are labeled VLD/S1,
DTY/S2, and WT/S3. The reason for the dual names is that
their functions vary, dependent on the state of the static Status
Function (SFUNC) input signal. When SFUNC is low, the
status bits are said to be in a “dedicated” mode and are
referred to as Valid, Dirty and Write-Through. See Figure 5.
When SFUNC is high, the status bits play no special role within
the 71215/16 and are simply referred to as Status 1, Status 2
and Status 3. See Figure 6. The functionality of VLD and WT
in the dedicated mode is described later. DTY/S2 does not
have any special functionality within the 71215/16.
WTIN / S3IN
DTYIN / S2IN
VLDIN / S1IN
I/O
Address
MEMORY V D WP
WET
WES
internal RESET
OE
COMPARE
WTOUT / S3OUT
DTYOUT / S2OUT
VLDOUT / S1OUT
CLK
71216 only
W/R (TT1)
BRDYH (TAH)
BRDY IN (TAIN )
BRDYOE (TAOE )
Figure 5. Dedicated Mode Logic (71216 pin names are in parenthesis)
5
MATCH
BRDY (TA )
3176 drw 05
5 Page 
A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216
APPLICATION NOTE AN-136
ADDR
PowerPC
TT1
TA
A0 - A28
A12 A13 - A26
(2) IDT71216
TAG RAM
A0 - A11
TAG (11:0)
ADDR (13:0)
MATCH
RESET
STATUSout
TT1
TA
VCC
STATUSin
TAOE
TAH
TAIN
CS2 WES
CS1 WET
OES OET
SFUNC
PWRDN
CS2
CS1
3
3
VARIOUS CONTROL SIGNALS
DATA
DH0 - DH31, DL0 - DL31, and DP0 - DP7
CHIP SET
MATCH
STATUS
STATUS
TAOE
TAH
WES
WET
OET
PWRDN
TA
A12 A13 - A28
VCC ADDR
CS2
CS1
64K x 18
BURST
SRAM
I/Os
ADDR
CS2
CS1
CACHE READ
and WRITE
64K x 18
BURST
SRAM
I/Os
MAIN MEMORY READ/WRITE
Figure 13: PowerPC / 71216 Example of 1 MB Cache
3176 drw 13
Figure 13 shows a 1MB cache for the PowerPC using the
71216. The implementation is essentially the same as for
512KB, but with two 71216 Tags and two banks of data
SRAMs. Except for CS1 and CS2, all the same signals that
were connected to the first Tag RAM should be connected to
the same pins of the second Tag RAM. The least significant
tag bit of the 512KB cache is used to select between the two
Tag RAMs of the 1MB cache. The same is true for the two
banks of data SRAMs. The tag field then shifts one bit in the
direction of the more significant address bits. Please note that
the PowerPC and Intel processors do not have the same
address sequence. A0 is the MSB for the PowerPC while A31
is the MSB for Intel's processors.
It is also possible to double the size of the cache and
cached address space without doubling up the Tag RAMs.
This can be done by doubling the line size of the cache - from
32 bytes to 64 bytes, for example. It is not necessary to have
the same line size for both the primary and secondary caches,
though it does simplify the cache controller. A more detailed
discussion of this topic is beyond the scope of this application
note.
The CLK pin should be driven by the same clock that drives
the CPU. Although there is no standard for clock skew
tolerances between devices, a recommended target is ±1nS.
MESI PROTOCOL IMPLEMENTATION
MESI is a cache coherency protocol, implemented in the
primary cache of both the PowerPC 601 and the Pentium
Processor. With the 71215/16, it is now practical to also
implement MESI for the L2 cache. The acronym stands for
Modified (write-back data that is dirty), Exclusive (clean write-
back data that can later transition to Modified), Shared (write-
through data which cannot become Modified) and Invalid. In
short, it allows for cache lines to be individually marked as
11
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