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PDF AN2635 Data sheet ( Hoja de datos )
| Número de pieza | AN2635 | |
| Descripción | On-Chip FLASH Programming Routines | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Application Note
AN2635
Rev. 4, 10/2005
On-Chip FLASH Programming
Routines
For MC68HC908LB8, MC68HC908QL4, MC68HC908QB8,
MC68HC908QB4, MC68HC908QY8, and MC68HC908QY4A Series1
By: Kazue Kikuchi
MCU Applications Engineering
Austin, Texas
Introduction
This application note applies to the MC68HC908LB8, MC68HC908QL4, MC68HC908QB4/QB8/QY8,
and MC68HC908QY4A Series1 FLASH-based microcontroller units (MCUs). To program, erase, and
verify FLASH, these MCUs have on-chip FLASH support routines residing in ROM (read-only memory).
These routines may be accessed in either user mode or monitor mode and eliminate the need to develop
separate FLASH routines for applications.
This application note describes how to call each of the routines in user software, what is performed, and
what is returned as confirmation of routine execution. The software files are available as a zip file,
AN2635SW, from the Freescale Semiconductor website: www.freescale.com
NOTE
With the exception of mask set errata documents, if any other
Freescale Semiconductor document contains information that conflicts with
the information in the device data sheet, the data sheet should be
considered to have the most current and correct data.
1. MC68HC908QY4A Series includes MC68HC908QY4A, MC68HC908QY2A, MC68HC908QY1A, MC68HC908QT4A,
MC68HC908QT2A, MC68HC908QT1A
© Freescale Semiconductor, Inc., 2005. All rights reserved.
1 page  
How to Use the Routines
Table 3. Summary of On-Chip FLASH Support Routines
GetByte
PutByte
RDVRRNG PRGRNGE ERARNGE
DELNUS
Get a data byte Send a data
Routine
Description
serially through
byte serially
PTA0
through PTA0
Read and/or
verify
a FLASH
range
Program a
FLASH range
(maximum 32
bytes in a row)
Erase a PAGE
or entire array
Generate
delay
3×A×X+8
(cycles)
Internal
Operating
Frequency
(fop)
—
—
Hardware
Requirement
Pullup on PTA0
Pullup on PTA0
—
For send-out
option, pullup
on PTA0
1 MHz to
8.4 MHz
N/A
1 MHz to
8.4 MHz
N/A
—
N/A
Entry
Conditions
H:X: First
address of
range
LADDR: Last
address of
PTA0: Input
(DDRA0 = 0)
PTA0: Input
and 0 data bit
(DDRA0 = 0,
PTA0 = 0)
A: data to be
sent
range
A: A = $00 for
send-out
option or
A ≠ $00 for
verify option
For send-out
option
PTA0: Input
and 0 data bit
(DDRA0 = 0,
PTA0 = 0)
For verify
option,
DATA array:
H:X: First
address
of range
LADDR: Last
address of
range
CPUSPD: the
nearest
integer fop (in
MHz) times 4
Data array:
Load data
to be
programmed
H:X: Address
within a page
or an array to
be erased
CPUSPD: the
nearest
integer fop (in
MHz) times 4
CTRLBYT:
$40 = MASS
erase
$00 = PAGE
erase
A: Value
between
4 and 255
X: Value
between
1 and 255
Load data to
be verified
against
FLASH read
data
Freescale Semiconductor
On-Chip FLASH Programming Routines, Rev. 4
5
5 Page 
Example 4: Send-Out Option
Example 4 shows how to use the send-out option:
RDVRRNG equ $0384
bclr 0,DDRA
bclr 0,PTA
ldhx #$C025
sthx LADDR
ldhx #$C010
clra
jsr RDVRRNG
;LB8 RDVRRNG jump address
;Configure Port A bit 0 as an input
;Initialize data bit to zero PTA0=0
;Load last address of range to
; LADDR
;Load beginning address of range
; to H:X
;A=0 to select send-out option
;Call RDVRRNG routine
; A contains a checksum value
How to Use the Routines
PRGRNGE
PRGRNGE is used to program a range of FLASH locations with data loaded into the DATA array. The
range must be less-than or equal-to 32 bytes. All bytes that will be programmed must be in the same row.
Programming data is passed to PRGRNGE in the DATA array. The size of the DATA array must match
the size of a specified programming range. This routine supports an internal operating frequency between
1.0 MHz and 8.4 MHz.
For this split-gate FLASH, the programming algorithm requires a programming time (tprog) between 30 µs
and 40 µs. (Refer to the FLASH memory section in the device data sheet.) Table 4 shows how tprog is
adjusted by a CPUSPD value in this routine. The CPUSPD value is the nearest integer of fop (in MHz)
multiplied by 4. For example, if fop is 2.4576 MHz, the CPUSPD value is 10 ($0A). If fop is 8.0 MHz, the
CPUSPD value is 32 ($20).
Case 1
Case 2
Table 4. tprog vs. Bus Frequency
Operating Bus Freq. (fop)
1.0 MHz ≤ fBus < 1.125 MHz
1.125 MHz ≤ fBus ≤ 8.4 MHz
CPUSPD
4
5 to 34
tprog (Cycles)
38
8 x CPUSPD + 5
tprog
33.8 µs < tprog ≤ 38.0 µs
32.1 µs ≤ tprog ≤ 40.0 µs
In PRGRNGE, the high programming voltage time is enabled for less than 125 µs when programming a
single byte at any operating bus frequency between 1.0 MHz and 8.4 MHz. Therefore, even when a row
is programmed by 32 separate single-byte programming operations, the cumulative high voltage
programming time is less than the maximum tHV (4 ms). The tHV is defined as the cumulative high voltage
programming time to the same row before the next erase. For more information, refer to the memory
characteristics in the electrical specifications section of the device data sheet.
This routine does not confirm that all bytes in the specified range are erased prior to programming. Nor
does this routine perform a verification after programming, so there is no return confirmation that
programming was successful. To program data successfully, the user software is responsible for these
Freescale Semiconductor
On-Chip FLASH Programming Routines, Rev. 4
11
11 Page | ||
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| PDF Descargar | [ Datasheet AN2635.PDF ] | |
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