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PDF HT46C63 Data sheet ( Hoja de datos )
| Número de pieza | HT46C63 | |
| Descripción | A/D with LCD Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT46R63/HT46C63
A/D with LCD Type 8-Bit MCU
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Operating frequency: External RC or Crystal
· 32.768kHz crystal oscillator used for timing purposes
· Watchdog enable or disable function
· 1x16 bits timer with an overflow interrupt (TMR)
· Time base generator (clock source: 32.768kHz)
and RTC interrupts
· 4K´15 program memory
· 208´8 data memory RAM
· Maximum of 32 I/O lines (shared with INT0, INT1,
TMR, AN0~AN7, PWM0~PWM3)
· 8-level stack
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· 2 external interrupts (high/low going trigger)
· One comparator
· LCD: 20´3 or 19´4, 1/3 bias with 12 pins logical
outputs options. (select by options in unit of 4 pins, ´8
high sink)
· Built-in R type bias generator
· 8 channels 8-bits resolution A/D converter
· 4 channels PWM outputs
· 56-pin SSOP, 100-pin QFP package
General Description
The HT46R63/HT46C63 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D product applications that interface di-
rectly to analog signals and which require LCD Inter-
face. The mask version HT46C63 is fully pin and
functionally compatible with the OTP version HT46R63
device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, multi-channel A/D
Converter, Pulse Width Modulation function, HALT and
wake-up functions, in addition to a flexible and
configurable LCD interface enhance the versatility of
these devices to control a wide range of applications re-
quiring analog signal processing and LCD interfacing,
such as electronic metering, environmental monitoring,
handheld measurement tools, motor driving, etc., for
both industrial and home appliance application areas.
Rev. 1.90
1 May 17, 2004
1 page  
HT46R63/HT46C63
Pin Name I/O
Option
Description
OSC1
OSC2
I
O
RC or crystal
A resistor across OSC1 and VDD or a crystal across OSC1 and OSC2 will
generate a system clock.
OSC3
OSC4
I
O
¾
32768Hz crystal across OSC3 and OSC4 will generate RTC clock signal
which only provides system timing.
CMPN
I ¾ Negative input for comparator
CMPP
I ¾ Positive input for comparator
CMPO
O ¾ Comparator output
CHGO
O ¾ Comparator output with 32768Hz carrier
VDD
¾ ¾ Positive power supply
AVDD
¾
¾
A/D converter Positive power supply, AVDD should be externally con-
nected to VDD
VSS
¾ ¾ Negative power supply, ground
RES
I ¾ Schmitt trigger reset input
VLCD
I/O ¾ LCD highest voltage; should be connected to VDD with external resistor.
SEG0~SEG18
O
SEG7~SEG18
logical CMOS
LCD segment signal driving outputs SEG7~SEG10 can be optioned as out-
put lines. SEG11~SEG14, SEG15~SEG18 can be optioned as a high sink-
ing output lines.
COM0~COM2
COM3/SEG19
O
COM3 or
SEG19
LCD common signal driving outputs
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Symbol
Parameter
VDD Operating Voltage
Test Conditions
VDD Conditions
fSYS=4MHz
¾
fSYS=8MHz
IDD1
Operating Current (RC OSC)
(Analog Circuit Disabled)
3V
No load, fSYS=4MHz
5V
IDD2
Operating Current
(RC OSC)
3V
No load, fSYS=4MHz
5V
IDD3 Operating Current
5V No load, fSYS=8MHz
ISTB1
Standby Current
3V No load,
(WDT OSC On, RTC Off, LCD Off) 5V System HALT
ISTB2
Standby Current
(WDT OSC Off, RTC Off, LCD Off)
3V
System HALT
5V
Min.
2.2
3.3
¾
¾
¾
¾
¾
¾
¾
¾
¾
Typ.
¾
¾
1
3
1
3
3
¾
¾
¾
¾
Ta=25°C
Max. Unit
5.5 V
5.5 V
2
mA
5
2
mA
5
5 mA
5
mA
15
1
mA
1
Rev. 1.90
5 May 17, 2004
5 Page 
HT46R63/HT46C63
Labels
C
AC
Z
OV
PDF
TO
¾
Bits Function
C is set if an operation results in a carry during an addition operation or if a borrow does not take
0 place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
1
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
2 Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
3
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the high-
est-order bit, or vice versa; otherwise OV is cleared.
4
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by exe-
cuting the ²HALT² instruction.
5
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set
by a WDT time-out.
6, 7 Unused bit, read as ²0²
Status Register
Bank Pointer
The bank pointer is used to assign the accessed RAM
bank. When the users want to access the RAM bank ²0²
a 0 should be loaded onto BP. When the BP is equal to
²1², the LCD RAM will be accessed (use MP1/R1 indi-
rect addressing only). RAM locations before 40H in any
bank are overlapped.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addi-
tion operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² in-
struction. The PDF flag can be affected only by exe-
cuting the ²HALT² or ²CLR WDT² instruction or a
system power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
Interrupt
The microcontroller provides two external interrupts, an
internal timer/event counter overflow interrupt, a time
base time-out interrupt, an A/D converter
end-of-conversion interrupt and a real time clock
time-out interrupt. The interrupt control registers
(INTC0: 0BH and INTC1: 1EH) contains the interrupt
control bits to set the enable or disable and the interrupt
request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flags are recorded. If a certain
interrupt requires servicing within the service routine,
the programmer may set the EMI and the corresponding
bit of INTC0/INTC1 to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the SP is de-
creased. If immediate service is desired, the stack has
to be prevented from becoming full.
Rev. 1.90
11 May 17, 2004
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT46C63.PDF ] | |
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