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PDF HT49CV9 Data sheet ( Hoja de datos )
| Número de pieza | HT49CV9 | |
| Descripción | A/D | |
| Fabricantes | Holtek Semiconductor | |
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HT49RV9/HT49CV9
A/D With VFD Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0077E HT49CVX Remote Control Receiver SWIP Design Note
- HA0078E HT49CVX Display SWIP Design Note
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· 32 bidirectional I/O lines (PA, PB, PC, PD)
· Two external interrupt inputs
· Two 16-bit programmable timer/event counters with
PFD (programmable frequency divider) function
· One 8-bit Remote Control Timer (RMT)
· Single channel serial interface
· VFD driver with 12´16 segments
(12-segment & 16-grid to 20-segment & 8-grid)
· 8K´16´2 program memory
· 192´8´4 data memory RAM
· Supports PFD for sound generation
· Real Time Clock (RTC), 32768Hz with quick start-up
control bit
· 8-bit prescaler for RTC
· Watchdog Timer
· Buzzer output
· On-chip crystal, RC and 32768Hz crystal oscillator
· HALT function and wake-up feature reduce power
consumption
· 16-level subroutine nesting
· 8-channel 10-bit resolution A/D converter
· 4-channel 8-bit PWM output shared with 4 I/O lines
· LVR function with enable/disable function
· Bit manipulation instruction
· 16-bit table read instruction
· Up to 0.5ms instruction cycle with 8MHz system clock
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· 100-pin QFP package
General Description
The HT49RV9/HT49CV9 are 8-bit high performance
single chip MCUs. Their single cycle instruction and
2-stage pipeline architecture make them suitable for
high speed applications. As the devices include an VFD
driver they are suitable for use in products which require
a front panel for their operation such as DVDs, VCDs,
Mini-component audio systems, cassette decks, tuners,
CD players, other home appliances, etc.
Rev. 1.00
1 April 20, 2006
1 page  
HT49RV9/HT49CV9
D.C. Characteristics
Symbol
Parameter
VDD Operating Voltage
Test Conditions
VDD Conditions
¾ fSYS=4MHz
¾ fSYS=8MHz
VEE VFD Supply Voltage ¾ ¾
IDD1
3V No load, ADC off
Operating Current (Crystal OSC) 5V VFD off, fSYS=4MHz
IDD2
Operating Current (RC OSC)
3V No load, ADC off
5V VFD off, fSYS=4MHz
IDD3
Operating Current
(fSYS=32768Hz)
3V No load, ADC off
5V VFD off
IDD4
3V No load, ADC off
Operating Current (Crystal OSC) 5V VFD on, , fSYS=4MHz
ISTB1 Standby Current (*fS=T1)
3V No load, system HALT
5V VFD off at HALT
ISTB2
Standby Current
(*fS=32768Hz OSC)
3V No load, system HALT
5V VFD off at HALT
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾
VIL2
VIH2
VLVR
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset Voltage
¾¾
¾¾
LVR voltage 3.0V option
¾
LVR voltage 3.8V option
IOL
I/O Port Segment Logic Output
Sink Current
3V
VOL=0.1VDD
5V
IOH1
I/O Port Segment Logic Output
Source Current
3V
VOH=0.9VDD
5V
IOH2 Segment/Grid Source Current 5V VOH=VDD-2V
RPH
Pull-high Resistance of I/O Ports 3V
and INT0, INT1, RMT
5V
¾
¾
VAD A/D Input Voltage
EAD
A/D Conversion Integral
Nonlinearity Error
¾
¾
¾
¾
IADC
Additional Power Consumption
if A/D Converter is Used
3V
5V
¾
Ta=25°C
Min. Typ. Max. Unit
2.2 ¾ 5.5
V
3.3 ¾ 5.5
V
0 ¾ VDD-30 V
¾2
3 mA
¾5
8 mA
¾ 1.8 2.7 mA
¾ 4.6 7.5 mA
¾ 1.2 2 mA
¾4
7 mA
¾4
6 mA
¾ 7 15 mA
¾ ¾ 1 mA
¾ ¾ 2 mA
¾ 4 10 mA
¾ 14 20 mA
0 ¾ 0.2VDD V
0.8VDD ¾ VDD V
0 ¾ 0.4VDD V
0.9VDD ¾ VDD V
2.7 3.0 3.3
V
3.5 3.8 4.0
V
6 12 ¾ mA
10 25 ¾ mA
-2 -4 ¾ mA
-5 -8 ¾ mA
-15 ¾
¾ mA
40 60 80 kW
10 30 50 kW
0 ¾ VDD V
¾ ±0.5 ±1 LSB
¾1
¾2
2 mA
4 mA
Note: ²*fS² Refer to WDT clock option
Rev. 1.00
5 April 20, 2006
5 Page 
HT49RV9/HT49CV9
Interrupts
The devices provides two external interrupts, two inter-
nal timer/event counter interrupts, three remote control
timer interrupts, an internal real time clock interrupt and
serial interface interrupt. The interrupt control register 0
(INTC0;0BH) and interrupt control register 1
(INTC1;1EH) both contain the interrupt control bits that
are used to set the enable/disable status and interrupt
request flags.
Once an interrupt subroutine is serviced, all other inter-
rupts are blocked (by clearing the EMI bit). This scheme
may prevent any further interrupt nesting. Other inter-
rupt requests may take place during this interval, but
only the interrupt request flag will be recorded. If another
interrupt requires servicing while the program is in the
interrupt service routine, the programmer should set the
EMI bit and the corresponding bit of the INTC0 or INTC1
to allow interrupt nesting. Once the stack is full, the inter-
rupt request will not be acknowledged, even if the related
interrupt is enabled, until the SP is decremented. If imme-
diate service is desired, the stack should be prevented
from becoming full.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the Program Counter onto the
stack followed by a branch to a subroutine at the speci-
fied location in the ROM. Only the contents of the Pro-
gram Counter is pushed onto the stack. If the contents of
the register or of the status register (STATUS) is altered
by the interrupt service program which corrupts the de-
sired control sequence, the contents should be saved in
advance.
External interrupts are triggered by an edge transition of
INT0 or INT1 (configuration option: high to low, low to
high, low to high or high to low), and the related interrupt
request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0)
is set as well. After the interrupt is enabled, the stack is
not full, and the external interrupt is active, a subroutine
call to location 04H or 08H occurs. The interrupt request
flag (EIF0 or EIF1) and EMI bits are all cleared to disable
other maskable interrupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 6 of INTC0), which is normally
caused by a timer overflow. After the interrupt is en-
abled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 0CH occurs. The related inter-
rupt request flag (T0F) is reset, and the EMI bit is
cleared to disable other maskable interrupts.
Timer/Event Counter 1 is operated in the same manner
but its related interrupt request flag is T1F (bit 4 of
INTC1) and its subroutine call location is 10H.
The Serial Interface interrupt is initialized by setting the
interrupt request flag (TDRF; bit 5 of INTC1), that is
caused by completely receiving/transferring 8 bits of
data from a serial interface. After the interrupt is en-
abled, and the stack is not full, and the TRF bit is set, a
subroutine call to location 14H occurs. The related inter-
rupt request flag (TDRF) is reset and the EMI bit is
cleared to disable further maskable interrupts.
The multi-function interrupt is initialized by setting the in-
terrupt request flag (MFF; bit 6 of INTC1), that is caused
by a regular real time clock signal, caused by a rising
edge of RMT, or caused by a falling edge of RMT or
caused by an RMT overflow. After the interrupt is en-
abled, the stack is not full, and the MFF bit is set, a sub-
routine call to location 18H occurs. The related interrupt
request flag (MFF) is reset and the EMI bit is cleared to
disable further maskable interrupts.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the ²RETI² instruction is executed or the EMI bit and the
related interrupt control bit are both set to 1 (if the stack
is not full). To return from the interrupt subroutine, ²RET²
or ²RETI² may be invoked. RETI sets the EMI bit and en-
ables an interrupt service, but RET does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit.
Interrupt Source
Priority Vector
External interrupt 0
1 04H
External interrupt 1
2 08H
Timer/Event Counter 0 overflow
3
0CH
Timer/Event Counter 1 overflow
4
10H
Serial interface interrupt
5 14H
Multi-function interrupt
6 18H
The RMT overflow interrupt flag (RMTVF; bit 0 of MFIS),
real time clock interrupt flag (RTF; bit 1 of MFIS), the
RMT rising edge interrupt flag (RMT0F; bit 2 of MFIS)
and the RMT falling edge interrupt flag (RMT1F; bit 3 of
MFIS) indicate that a related interrupt has occurred. Af-
ter reading these flags, these flags will not be cleared
automatically, they should be cleared by the user.
The serial interface interrupt is indicated by the interrupt
flag (TDRF; bit 5 of INTC1), that is caused by receiving
or transferring a complete 8-bit data transfer between
the HT49RV9/ HT49CV9 and an external device. After
the interrupt is enabled (by setting ESBI; bit 1 of INTC1),
and the stack is not full, a subroutine call to location 14H
occurs.
The Timer/Event Counter 0 interrupt request flag (T0F),
external interrupt 1 request flag (EIF1), external inter-
rupt 0 request flag (EIF0), enable Timer/Event Counter0
interrupt bit (ET0I), enable external interrupt 1 bit (EEI1),
Rev. 1.00
11 April 20, 2006
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT49CV9.PDF ] | |
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