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AD9212 の電気的特性と機能

AD9212のメーカーはAnalog Devicesです、この部品の機能は「Serial LVDS A/D Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD9212
部品説明 Serial LVDS A/D Converter
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD9212 Datasheet, AD9212 PDF,ピン配置, 機能
Data Sheet
Octal, 10-Bit, 40 MSPS/65 MSPS,
Serial LVDS, 1.8 V ADC
AD9212
FEATURES
8 analog-to-digital converters (ADCs) integrated into 1 package
100 mW ADC power per channel at 65 MSPS
SNR = 60.8 dB (to Nyquist)
ENOB = 9.8 bits
SFDR = 80 dBc (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical); INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
325 MHz, full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9212 is an octal, 10-bit, 40 MSPS/65 MSPS ADC with an
on-chip sample-and-hold circuit designed for low cost, low power,
small size, and ease of use. Operating at a conversion rate of up to
65 MSPS, it is optimized for outstanding dynamic performance
and low power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO)
for capturing data on the output and a frame clock (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD DRGND
VIN + A
VIN – A
VIN + B
VIN – B
VIN + C
VIN – C
VIN + D
VIN – D
VIN + E
VIN – E
VIN + F
VIN – F
VIN + G
VIN – G
VIN + H
VIN – H
VREF
SENSE
REFT
REFB
AD9212
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
REF
SELECT
0.5V
SERIAL PORT
INTERFACE
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
DATA RATE
MULTIPLIER
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
D+E
D–E
D+F
D–F
D+G
D–G
D+H
D–H
FCO+
FCO–
DCO+
DCO–
RBIAS AGND CSB
SDIO/ SCLK/
ODM DTP
Figure 1.
CLK+
CLK–
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9212 is available in a RoHS-compliant, 64-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight ADCs are contained in a small package.
2. Low Power of 100 mW per Channel at 65 MSPS.
3. Ease of Use. A data clock output (DCO) operates up to
300 MHz and supports double data rate (DDR) operation.
4. User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9222 (12-bit)
and AD9252 (14-bit).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.

1 Page





AD9212 pdf, ピン配列
AD9212
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Product Highlights ........................................................................... 1 
Revision History ............................................................................... 3 
Specifications..................................................................................... 4 
AC Specifications.......................................................................... 5 
Digital Specifications ................................................................... 6 
Switching Specifications .............................................................. 7 
Timing Diagrams.......................................................................... 8 
Absolute Maximum Ratings.......................................................... 10 
Thermal Impedance ................................................................... 10 
ESD Caution................................................................................ 10 
Pin Configuration and Function Descriptions........................... 11 
Equivalent Circuits ......................................................................... 13 
Typical Performance Characteristics ........................................... 15 
Theory of Operation ...................................................................... 20 
Analog Input Considerations.................................................... 20 
Data Sheet
Clock Input Considerations...................................................... 23 
Serial Port Interface (SPI).............................................................. 31 
Hardware Interface..................................................................... 31 
Memory Map .................................................................................. 33 
Reading the Memory Map Table.............................................. 33 
Reserved Locations .................................................................... 33 
Default Values ............................................................................. 33 
Logic Levels................................................................................. 33 
Applications Information .............................................................. 36 
Design Guidelines ...................................................................... 36 
Evaluation Board ............................................................................ 37 
Power Supplies ............................................................................ 37 
Input Signals................................................................................ 37 
Output Signals ............................................................................ 37 
Default Operation and Jumper Selection Settings................. 38 
Alternative Analog Input Drive Configuration...................... 39 
Outline Dimensions ....................................................................... 56 
Ordering Guide .......................................................................... 56 
Rev. E | Page 2 of 56


3Pages


AD9212 電子部品, 半導体
Data Sheet
AD9212
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 35 MHz
fIN = 70 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 35 MHz
fIN = 70 MHz
WORST OTHER (EXCLUDING SECOND OR THIRD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—
AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz
fIN1 = 70 MHz, fIN2 = 71 MHz
AD9212-40
AD9212-65
Temperature Min Typ Max Min Typ Max Unit
Full 61.2 60.8 dB
Full 60.2 61.2
60.8 dB
Full 61.2 58.5 60.8 dB
Full 61.0 60.7 dB
Full 61.2 60.7 dB
Full 60.0 61.0
60.6 dB
Full 61.0 57.0 60.5 dB
Full 60.8 60.4 dB
Full 9.87 9.81 Bits
Full 9.71 9.87
9.81 Bits
Full 9.87 9.43 9.81 Bits
Full 9.84 9.79 Bits
Full 87 81 dBc
Full 72 85
79 dBc
Full 79 62 77 dBc
25°C
69 77
dBc
Full 74 72 dBc
Full −87 −81 dBc
Full −85 −72 −79 dBc
Full −79 −77 −62 dBc
25°C −77 −69 dBc
Full −74 −72 dBc
Full −90 −86 dBc
Full −85 −72 −86 dBc
Full −85 −85 −70 dBc
Full −85 −85 dBc
25°C 80.0 77.0 dBc
25°C 77.0 77.0 dBc
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. E | Page 5 of 56

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共有リンク

Link :


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