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PI6C105 の電気的特性と機能

PI6C105のメーカーはPericom Semiconductorです、この部品の機能は「Precision Clock Synthesizer」です。


製品の詳細 ( Datasheet PDF )

部品番号 PI6C105
部品説明 Precision Clock Synthesizer
メーカ Pericom Semiconductor
ロゴ Pericom Semiconductor ロゴ 




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PI6C105 Datasheet, PI6C105 PDF,ピン配置, 機能
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PI6C105111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222
Precision Clock Synthesizer
for Mobile PCs
Features
Two copies of CPU clock with VDD of 2.5V ±5%
100 MHz or 66 MHz operation
Six copies PCI clock (synchronous with CPU clock) 3.3V
One copy of Ref. clock @ 14.31818 MHz (3.3VTTL)
48 MHz USB Clock, 24 MHz Super I/O clock
I2C Serial Configuration Interface
Spread Spectrum Modulation for CPUCLK, and PCICLK
Low-cost 14.31818 MHz crystal oscillator input
Power management control
Isolated core VDD, VSS pins for noise reduction
28-pin SSOP and SOIC package (H)
Description
The PI6C105 is a high-speed, low-noise clock generator designed
to work with the PI6C18x family of clock buffers to meet all clock
needs for Mobile Intel Architecture platforms. CPU and chipset
clock frequencies of 66.6 MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs. 2.5V signaling follows JEDEC standard
8-X. Power sequencing of the 3.3V and 2.5V supplies is not
required.
An asynchronous PWR_DWN# signal may be used to power down
(or up) the system in an orderly manner.
Block Diagram
Pin Configuration
XTAL_IN
XTAL_OUT
Spread#
SEL100/66#
S DATA
SCLK
REF
OSC
PLL1
I2C
PLL2
CPU_STOP#
DIV
PCI_STOP#
÷2
REF
2 CPUCLK
[0:1]
5 PCICLK
[1:5]
PCICLK_F
48 MHz
24 MHz
XTAL_IN
XTAL_OUT
V SSPCI
PCICLK_F
PCICLK1
PCICLK2
PCICLK3
PCICLK4
V DDPCI
PCICLK5
V DDP 2
48M/SPREAD#
V SSP 2
24M/SEL100/66#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 V SSREF
27 V DDREF
26 REF
25 V DDCPU
24 CPUCLK0
28-Pin 23 CPUCLK1
H
22 V SSCPU
21 V DDCORE
20 V SSCORE
19 PCI_STOP#
18 CPU_STOP#
17 PWR_DWN#
16 S DATA
15 SCLK
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PI6C105 pdf, ピン配列
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PI6C105
111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888P999000r111e222c333444is555666i777o888n999000111C222111l222o333c444555k666777S888999y000111n222t333h444555e666777s888i999z000e111r222333f444555o666r777888M999000111o222111b222i333l444e555666P777888C999000111s222
Select Functions
SEL100/66# Function
0 66 MHz active
1 100 MHz active
Clock Enable Configuration
CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK [0:1] PCICLK [1:5] PCICLK_F Other Clocks Crystal
XX
0
low
low
low
stopped
off
00
1
low
low
33 MHz
running
running
01
1
low
33 MHz
33 MHz
running
running
10
1
100/66 MHz
low
33 MHz
running
running
11
1
100/66 MHz
33 MHz
33 MHz
running
running
VCO's
off
running
running
running
running
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C105 is a slave receiver device. It can not be read back.
Sub addressing is not supported. To change one of the control
bytes, all preceding bytes must be sent.
Every byte put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers, SDATA changes only when SCLK is
LOW. Exceptions: A HIGH-to-LOW transition on SDATA while
SCLK is HIGH indicates a “start” condition. A LOW-to-HIGH
transition on SDATA, while SCLK is HIGH, is a “stop” condition
and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended
with a stop condition. The first byte after a start condition is always
a 7-bit address byte followed by a read/write bit. (HIGH = read
from addressed device, LOW= write to addressed device). If the
device’s own address is detected, PI6C105 generates an acknowl-
edge by pulling SDATA line LOW during ninth clock pulse, then
accepts the following data bytes until another start or stop condi-
tion is detected.
Following acknowledgment of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
PI6C105 I2C Address Assignment
A7 A6 A5 A4 A3 A2
110 100
A1
1
A0
0
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PI6C105 電子部品, 半導体
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PI6C105
111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888P999000r111e222c333444is555666i777o888n999000111C222111l222o333c444555k666777S888999y000111n222t333h444555e666777s888i999z000e111r222333f444555o666r777888M999000111o222111b222i333l444e555666P777888C999000111s222
SEL100/66# (pin 14) SS1 Byte3 [6] SS0 Byte3 [5] Down Spread
Description
0 0 0 -0.6% 66.6 MHz, -0.6% down spread
0 0 1 -1.2% 66.6 MHz, -1.2% down spread
0 1 0 -1.8% 66.6 MHz, -1.8% down spread
0 1 1 -2.4% 66.6 MHz, -2.4% down spread
1 0 0 -0.6% 100 MHz, -0.6% down spread
1 0 1 -1.0% 100 MHz, -1.0% down spread
1 1 0 -1.5% 100 MHz, -1.5% down spread
1 1 1 -2.0% 100 MHz, -2.0% down spread
Power Management Timing
Signal
Signal State
Latency
No. of rising edges of free running PCICLK
CPU_STOP#
0 (disabled)
1
1 (enabled)
1
PCI_STOP#
0 (disabled)
1
1 (enabled)
1
PWR_DWN# 1 (normal operation)
3ms
0 (power down)
2 max.
Notes:
1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs
between when the clock disable goes low/high to when the first valid clock comes out of
the device.
2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid
clocks are driven from the device.
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共有リンク

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