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PDF ST72334J Data sheet ( Hoja de datos )
| Número de pieza | ST72334J | |
| Descripción | (ST72314J / ST72124J / ST72334J) 8-BIT MCU | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST72334J/N,
ST72314J/N, ST72124J
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
PRELIMINARY DATA
s Memories
– 8K or 16K Program memory (ROM or single
voltage FLASH) with read-out protection and
in-situ programming (remote ISP)
– 256 bytes EEPROM Data memory (with read-
out protection option in ROM devices)
– 384 or 512 bytes RAM
s Clock, Reset and Supply Management
– Enhanced reset system
– Enhanced low voltage supply supervisor with
3 programmable levels
– Clock sources: crystal/ceramic resonator os-
cillators or RC oscillators, external clock,
backup Clock Security System
– 4 Power Saving Modes: Halt, Active-Halt,
Wait and Slow
– Beep and clock-out capabilities
s Interrupt Management
– 10 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (4 vectors)
s 44 or 32 I/O Ports
– 44 or 32 multifunctional bidirectional I/O lines:
– 21 or 19 alternate function lines
– 12 or 8 high sink outputs
s 4 Timers
– Configurable watchdog timer
– Realtime base
– Two 16-bit timers with: 2 input captures (only
one on timer A), 2 output compares (only one
on timer A), External clock input on timer A,
PWM and Pulse generator modes
s 2 Communications Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
PSDIP56
PSDIP42
TQFP64
14 x 14
TQFP44
10 x 10
s 1 Analog Peripheral
– 8-bit ADC with 8 input channels (6 only on
ST72334Jx, not available on ST72124J2)
s Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
s Development Tools
– Full hardware/software development package
Device Summary
Feat ure s
ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4
Program memory - bytes
RAM (stack) - bytes
EEPROM - bytes
Peripherals
Operating Supply
CPU Frequency
Operating Temperature
P ac kages
8K 8K 16K 8K 16K 8K 16K
384 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256)
- - - - - 256 256
Watchdog, Two 16-bit Timers, SPI, SCI
- ADC
3.0V to 5.5 V
Up to 8 MHz (with up to 16 MHz oscillator)
-40°C to +85°C (-40°C to +105/125°C optional)
TQFP44 / SDIP42
TQFP64 / SDIP56
TQFP44 / SDIP42
8K
384 (256)
25 6
16 K
512 (256)
256
TQFP64 / SDIP56
Rev. 2.1
May 2000
1/148
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
1
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ST72334J/N, ST72314J/N, ST72124J
2 INTRODUCTION
The ST72334J/N, ST72314J/N and ST72124J de-
vices are members of the ST7 microcontroller fam-
ily. They can be grouped as follows:
– ST72334J/N devices are designed for mid-range
applications with Data EEPROM, ADC, SPI and
SCI interface capabilities.
– ST72314J/N devices target the same range of
applications but without Data EEPROM.
– ST72124J devices are for applications that do
not need Data EEPROM and the ADC peripher-
al.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set.
The ST72C334J/N, ST72C314J/N and
ST72C124J versions feature single-voltage
FLASH memory with byte-by-byte In-Situ Pro-
gramming (ISP) capability.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in Section 15 on page 105.
Figure 1. General Block Diagram
RESE T
ISP SEL
VDD
VSS
OSC 1
OSC 2
PF7,6,4,2:0
(6-BIT)
PE7:0
(6-BIT for N versions)
(2-BIT for J versions)
8-BIT CORE
ALU
CONTROL
LVD
MULTI OSC
+
CLOCK FILTER
MCC/RTC
PORT F
TIMER A
BEEP
PORT E
SCI
WATCHDOG
PROGRAM
MEMORY
(8K or 16K Bytes)
RAM
(384 or 512 Bytes)
EEPROM
(256 Bytes)
PORT A
PORT B
PORT C
TIMER B
SP I
PORT D
8-BIT ADC
PA7:0
(8-BIT for N versions)
(5-BIT for J versions)
PB7:0
(8-BIT for N versions)
(5-BIT for J versions)
PC7:0
(8-BIT)
PD7:0
(8-BIT for N versions)
(6-BIT for J versions)
VDDA
VSSA
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ST72334J/N, ST72314J/N, ST72124J
Pin n°
Pin Name
59 45 42 35 OSC1 3)
60 46 43 36 VDD_3
61 47 44 37 PE0/TDO
62 48 1 38 PE1/RDI
63 NC
64 NC
Level
I
S
I/O CT
I/O CT
Port
In put
Main
Output function
(after
reset)
Alternate function
XX
XX
External clock input or Resonator oscilla-
tor inverter input or resistor input for RC
oscillator
Digital Main Supply Voltage
X X Port E0 SCI Transmit Data Out
X X Port E1 SCI Receive Data In
Not Connected
Notes:
1. In the interrupt input column, “eix” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See Section 11 ”I/O PORTS” on page 37 and Section 15.8 ”I/O PORT PIN CHAR-
ACTERISTICS” on page 125 for more details.
3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to
the on-chip oscillator see Section 3 ”PIN DESCRIPTION” on page 6 and Section 15.5 ”CLOCK AND TIM-
ING CHARACTERISTICS” on page 113 for more details.
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