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Datasheet P3NB80FP PDF ( 特性, スペック, ピン接続図 )

部品番号 P3NB80FP
部品説明 STP3NB80FP
メーカ ST Microelectronics
ロゴ ST Microelectronics ロゴ 
プレビュー
Total 9 pages
		
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P3NB80FP Datasheet, P3NB80FP PDF,ピン配置, 機能
U.comwww.DataSheet4U.com
eet4®
STP3NB80
STP3NB80FP
ShN - CHANNEL 800V - 4.6- 2.6A - TO-220/TO-220FP
ata PowerMESHMOSFET
w.DTYPE
w STP3NB80
w STP3NB80FP
VDSS
800 V
800 V
RDS(on)
< 6.5
< 6.5
ID
2.6 A
2.6 A
s TYPICAL RDS(on) = 4.6
s EXTREMELY HIGH dv/dt CAPABILITY
s 100% AVALANCHE TESTED
ms VERY LOW INTRINSIC CAPACITANCES
os GATE CHARGE MINIMIZED
.cDESCRIPTION
Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an
Uadvanced family of power MOSFETs with
t4outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
elowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
eand switching characteristics.
hAPPLICATIONS
Ss HIGH CURRENT, HIGH SPEED SWITCHING
s UNINTERRUPTIBLE POWER SUPPLY(UPS)
tas DC-DC & DC-AC CONVERTERS FOR
TELECOM, INDUSTRIAL AND CONSUMER
aENVIRONMENT
.DABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
wVDS
wVDGR
VGS
wID
Drain-source Voltage (VGS = 0)
Drain- gate Voltage (RGS = 20 k)
Gate-source Voltage
Drain Current (continuous) at Tc = 25 oC
3
2
1
TO-220
3
2
1
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
Value
STP3NB80 STP3NB80FP
800
800
± 30
2.6 2.6 (••)
Unit
V
V
V
A
ID Drain Current (continuous) at Tc = 100 oC
IDM() Drain Current (pulsed)
Ptot Total Dissipation at Tc = 25 oC
Derating Factor
dv/dt(1) Peak Diode Recovery voltage slope
VISO Insulation Withstand Voltage (DC)
Tstg Storage Temperature
Tj Max. Operating Junction Temperature
() Pulse width limited by safe operating area
(••) Limited only by maximum temperature allowed
January 1999
1.6 1.6 (••)
m10.4
10.4
.co90 35
0.72
0.28
t4U4.5
e2000
e-65 to 150
h150
S(1) ISD 2.6 A, di/dt 200 A/µs, VDD V(BR)DSS, Tj TJMA
A
A
W
W/oC
V/ns
V
oC
oC
www.Data 1/9

1 Page



P3NB80FP pdf, ピン配列
www.DataSheet4U.com
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
td(on)
tr
Parameter
Turn-on Time
Rise Time
Test Conditions
VDD = 400 V ID = 1.3 A
RG = 4.7
VGS = 10 V
Qg Total Gate Charge
VDD =640 V ID = 3 A VGS = 10 V
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
SWITCHING OFF
Symbol
tr(Voff)
tf
tc
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
VDD = 640 V ID =3 A
RG = 4.7 VGS = 10 V
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
ISD
ISDM()
Source-drain Current
Source-drain Current
(pulsed)
VSD () Forward On Voltage
ISD = 2.6 A VGS = 0
trr Reverse Recovery
Time
Qrr Reverse Recovery
Charge
ISD = 2.6 A di/dt = 100 A/µs
VDD = 100 V Tj = 150 oC
IRRM
Reverse Recovery
Current
() Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
() Pulse width limited by safe operating area
STP3NB80/FP
Min.
Typ.
12
10
Max.
17
14
Unit
ns
ns
17 24 nC
6.5 nC
7.5 nC
Min.
Typ.
15
17
22
Max.
21
24
31
Unit
ns
ns
ns
Min.
Typ.
Max.
2.6
10.4
Unit
A
A
1.6
650
2.8
8.5
V
ns
µC
A
Safe Operating Area for TO-220
Safe Operating Area for TO-220FP
3/9


3Pages


P3NB80FP 電子部品, 半導体
STP3NB80/FP
www.DataSheet4U.com
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/9

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