DataSheet.jp

SA-1110 の電気的特性と機能

SA-1110のメーカーはIntel Corporationです、この部品の機能は「Intel-R StrongARM SA-1110 Microprocessor」です。


製品の詳細 ( Datasheet PDF )

部品番号 SA-1110
部品説明 Intel-R StrongARM SA-1110 Microprocessor
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 




このページの下部にプレビューとSA-1110ダウンロード(pdfファイル)リンクがあります。

Total 10 pages

No Preview Available !

SA-1110 Datasheet, SA-1110 PDF,ピン配置, 機能
www.DataSheet4U.com
Intel® StrongARM* SA-1110
Microprocessor
Product Features
Brief Datasheet
The Intel®StrongARM SA-1110 Microprocessor (SA-1110) is a device
optimized for meeting portable and embedded application requirements.
The SA-1110 incorporates a 32-bit StrongARM RISC processor capable of
running at up to 206 MHz. The SA-1110 has a large instruction and data
cache, memory-management unit (MMU), and read/write buffers. The
SA-1110 memory bus interfaces to many device types including
synchronous DRAM (SDRAM), synchronous mask ROM (SMROM), and
SRAM-like variable latency I/O devices with a shared data ready signal. In
addition, the SA-1110 provides system support logic, multiple serial
communication channels, a color/gray scale LCD controller, PCMCIA
support for up to two sockets, and general-purpose I/O ports.
s High performance
s Memory bus
150 Dhrystone 2.1 MIPS @ 133 MHz
235 Dhrystone 2.1 MIPS @ 206 MHz
Interfaces to ROM, synchronous mask
ROM (SMROM), Flash, SRAM,
SRAM-like variable latency I/O,
DRAM, and synchronous DRAM
(SDRAM)
s Low power (normal mode)
Supports two PCMCIA sockets
s 32-way set-associative caches
<240 mW @1.55 V/1D33atMaSHhzeet4U.com 16 Kbyte instruction cache
<400 mW @1.75 V/206 MHz
8 Kbyte write-back data cache
s Integrated clock generation
s 32-entry MMUs
Internal phase-locked loop (PLL)
Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
3.686-MHz oscillator
32.768-kHz oscillator
s Power-management features
s Write buffer
Normal (full-on) mode
8-entry, between 1 and 16 bytes each
Idle (power-down) mode
Sleep (power-down) mode
s Big and little endian operating modes s Read buffer
4-entry, 1, 4, or 8 words
s 3.3-V I/O interface
s 256 mini-ball grid array (mBGA)
Power dissipation, particularly in idle mode, is strongly dependent on the details of the
system design
DataShee
Order Number: 278241-005
April 2000
DataSheet4U.com
DataSheet4 U .com

1 Page





SA-1110 pdf, ピン配列
www.DataSheet4U.com
SA-1110
et4U.com
further power savings. For embedded applications, the SA-1110 offers high-performance
computing at consumer electronics pricing with MIPS-per-dollar and MIPS-per-watt advantages.
The SA-1110 delivers in price/performance and power/performance, making it a chice for portable
and embedded applications. The SA-1110 differs from the Intel® StrongARM SA-1100
Microprocessor (SA-1100) only in the features of its memory and PCMCIA controller.
Intel® StrongARM SA-1110 CPU
The SA-1110 CPU implements the ARM V4 architecture as defined in the ARM Architecture
Reference Manual. Architectural enhancements beyond the ARM V4 are implemented through use
of coprocessor 15. Control register reads and writes to coprocessor 15 provide access to MMU,
cache, and write and read buffer control registers.
The SA-1110 MMUs provide separate 32-entry translation look-aside buffers (TLBs) for the
instruction and data streams. Each of the 32 entries may map segments, large pages, or small pages
in memory. The SA-1110 contains 16 Kbyte of instruction cache and 8 Kbyte of data cache. In
addition to this, a minicache is provided to prevent periodic large data transfers from thrashing the
main data cache. The data and instruction caches are implemented as 32-byte blocks, and provide
32-way associativity, with victim replacement performed in a round-robin fashion. The minicache
is 16 entries and is 2-way set associative, implementing the least-recently-used (LRU) algorithm
for victim replacement.
The SA-1110 also provides a write buffer and a read buffer. The read buffer allows critical data to
be prefetched under software control, preventing pipeline stalls from occurring during external
memory reads. The write buffer provides additional system efficiency by buffering between the
CPU clock frequency and
memory. The write buffer
itsheeiDagchattutaeanSl tbhriueesse,stpa4neUed.dcawollmohwens
data is being
each entry to
written
contain
by the CPU to external
between 1 and 16 bytes.
The read buffer is four entries, and allows each entry to contain 1, 4, or 8 words.
Intel® StrongARM SA-1110 System Control Functions
The SA-1110 provides timers, sophisticated power-management functions, interrupt control, reset
control, and on-chip oscillators and PLLs for clock generation. There are 28 general-purpose I/Os,
which can, in addition to being directly read or written by the CPU, be programmed to generate an
interrupt.
The real-time clock and trim logic run off the 32.768-kHz crystal and provide accuracy of ±5
seconds/month.
The 32-bit OS timer runs off the 3.686-MHz oscillator and is used in companion with the four
32-bit timer match registers. One of the four match registers is used specifically as a watchdog
timer interrupt, preventing system lockout from occurring when software or hardware is trapped in
a loop state with no controlled exit. The remaining three registers are available for use as interval
timers or other user-defined purposes.
The interrupt controller routes all interrupt sources to either an FIQ or IRQ request to the CPU.
IRQ is a lower priority interrupt and may be interrupted by FIQ. FIQ is unique to the ARM
architecture and allows fast servicing to occur on specific interrupt sources, as determined by the
user. There are two levels in servicing interrupts. The first level alerts the user or operating system
to what specific module on the SA-1110 experienced an interrupt condition. The second level
provides information on what event within the specific module caused an interrupt to be flagged.
DataShee
DataSheet4U.com SA-1110 Brief Datasheet
3
DataSheet4 U .com


3Pages


SA-1110 電子部品, 半導体
www.DataSheet4U.com
SA-1110
et4U.com
Intel® StrongARM SA-1110 Power/Performance Benefits
The SA-1110 continues the StrongARM family of low-power performance. The SA-1110 takes
advantage of a 2.0-V nominal process technology. For processors running at 133 MHz, the
SA-1110 allows the core voltage to run at 1.55 V. Processors running at 206 MHz run at a core
voltage of 1.75 V. The I/O ring runs at 3.3 V to allow simple system interconnections. Another key
element in the SA-1110 power strategy is the use of independent conditional clocking trees, which
ensure that only currently required units are clocked and other units remain static. The SA-1110
may be run at a variety of frequencies, ranging from 39 MHz up to 206 MHz.
Table 1. SA-1110 Additional Features
133 MHz
206 MHz
Unit Performance
Supply
USB
IrDA
UART
Codec
LCD
Memory
Interrupt
150 MIPS
235 MIPS
1.55 V
12 Mbps
115 Kbps, 4 Mbps
230 Kbps
UCB1100, UCB1200, SPI, TI, µWire
1.75 V
12 Mbps
115 Kbps, 4 Mbps
230 Kbps
UCB1100, UCB1200, SPI, TI, µWire
1-, 2-, 4-, 8-, 12-, 16-bits/pixel
1-, 2-, 4-, 8-, 12-, 16-bits/pixel
EDO, DRAM, ROM, Flash, SRAM,
SMROM, and SDRAM
EDO, DRAM, ROM, Flash, SRAM, SMROM, and
SDRAM
FIQ, IRQ, Wake-up
FIQ, IRQ, Wake-up
DataSheet4U.com
DataShee
DataSheet4U.co6m
DataSheet4 U .com
SA-1110 Brief Datasheet

6 Page



ページ 合計 : 10 ページ
 
PDF
ダウンロード
[ SA-1110 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
SA-1110

Intel-R StrongARM SA-1110 Microprocessor

Intel Corporation
Intel Corporation


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap