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EK7601 の電気的特性と機能

EK7601のメーカーはEureka Microelectronicsです、この部品の機能は「240 Output Analog Source Driver For av Application Cof」です。


製品の詳細 ( Datasheet PDF )

部品番号 EK7601
部品説明 240 Output Analog Source Driver For av Application Cof
メーカ Eureka Microelectronics
ロゴ Eureka Microelectronics ロゴ 




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EK7601 Datasheet, EK7601 PDF,ピン配置, 機能
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EK7601 Data Sheet
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CONFIDENTIAL

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EK7601 pdf, ピン配列
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EUREKA
EK7601
240-Channel Analogue Source Driver
for colour TFT LCDs
OVERVIEW
The EM7601 is an analogue, fully colour, source driver for TFT LCD panels designed for camera,
TV etc. Analogue R, G and B signal are applied directly on the chip. For each of the 240 outputs,
the voltage is sampled and buffered to the panel. With a double sample and hold circuit a new
voltage can be sample whereas the previous sample voltage is applied to the panel.
According to different modes, the 3 input voltages (VA, VB, VC) can be applied on different output
to support various pixel array types.
The 3 input voltages (VA, VB, VC) can be sampled simultaneously or sequentially to have a
better flexibility with the input voltage. Using enable signal (STHx), several chips can be
cascaded for large panel.
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FEATURE
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LCD outputs: 240
Bi-directional shift (L/R)
Simultaneous or Sequential RGB acquisition mode
X1 or X3 clock mode
High frequency Sampling 10MHz (x1)
Automatic low power consumption mode after data capture (gated clock)
RGB colour selection (automatic or manual)
Applicable to COG / COF
Logic power supply voltage VDD: 2.7V – 5.25V
LCD power supply voltage AVDD: 4.5V – 5.5V
Output dynamic range AVSS+0.2V to AVDD-0.2V
Applicable to COG/COF
-2-
CONFIDENTIALRev 1.0 Feb.21.2002
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EK7601 電子部品, 半導体
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EUREKA
EK7601
3. PIN FUNCTION DESCRIPTION
Signal Name
Qa1 to Qa80
Qb1 to Qb80
Qc1 to Qc80
VA
VB
VC
L/R
STH1
STH2
CPH1
CPH2
CPH3
INH
Pin Type
Output
Function
Liquid-crystal application voltages
Each QaX, QbX or QcX correspond to one of the analogue
sample input signal VA, VB or VC.
Input
Video input signal
Analogue video input signal that is sampled internally and
applied to the panel.
Input
Bidir
Bidir
Input
(Pull-down
CPH2 & CPH3
@ TEST2 = L
And MODE=H)
Input
Controls the display data shift direction
L/R = H : STH1 input, Qa1Qc80, STH2 output.
L/R = L : STH2 input, Qc80Qa1, STH1 output.
Right shift start pulse
L/R = H : Becomes the start pulse input pin
L/R = L : Becomes the start pulse output pin
Left shift start pulse
L/R = H : Becomes the start pulse output pin
L/R = L : Becomes the start pulse input pin
Sampling clock input
Refers to the analogue data-sampling clock. The sampling
starts at the first rising edge of CPH1 when STH1 (L/R=H) is
activated.
CPH1 can be internally divided (x3 mode) to generate internal
clock signal CPH1’.
The sampling can be simultaneous or sequential.
In simDualttaaSnehoeuest4Um.ocdoem, the sampling is made during CPH1
(CPH1’) period for all output.
In sequential mode, the sampling is made according the table
below:
CPH1 (CPH1’) control the sampling for Qa1Qa80
CPH2 (CPH2’) control the sampling for Qb1Qb80
CPH3 (CPH3)’ control the sampling for Qc1Qc80
When clock mode x1 and sequential is selected, the three
inputs CPH1, CPH2 and CPH3 must have an input clock signal
applied. Otherwise only CPH1 must have input clock applied.
The clock selection table was described on the page 8.
Load line
The sampled voltages are connecting to the panel at the rising
edge of INH. The outputs of SHA(B) that was in sample mode
are applied to the panel, whereas the SHB(A) becomes ready
to sample new values.
During INH = L, output level is HiZ state and this signal initialise
the internal circuits.
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CONFIDENTIAL- 5 - Rev 1.0 Feb.21.2002
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共有リンク

Link :


部品番号部品説明メーカ
EK7601

240 Output Analog Source Driver For av Application Cof

Eureka Microelectronics
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EK7606

240 Output Analog Source Driver For av Application Cof / Cog

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