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IS93C86A の電気的特性と機能

IS93C86AのメーカーはISSIです、この部品の機能は「(IS93C76A / IS93C86A) 8K-BIT/16K-BIT SERIAL ELECTRICALLY ERASABLE PROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS93C86A
部品説明 (IS93C76A / IS93C86A) 8K-BIT/16K-BIT SERIAL ELECTRICALLY ERASABLE PROM
メーカ ISSI
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IS93C86A Datasheet, IS93C86A PDF,ピン配置, 機能
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IS93C76A IS93C86A
ISSI ®
8K-BIT/16K-BIT SERIAL ELECTRICALLY
ERASABLE PROM
Preliminary Information
MAY 2005
FEATURES
DESCRIPTION
• Industry-standard Microwire Interface
— Non-volatile data storage
— Low voltage operation:
Vcc = 1.8V to 5.5V -2
Vcc = 2.5V to 5.5V -3
— Full TTL compatible inputs and outputs
— Auto increment for efficient data dump
• User Configured Memory Organization
— By 16-bit or by 8-bit
IS93C76A/86A are 8kb/16kb non-volatile, ISSI ®
serial EEPROMs. They are fabricated using an
enhanced CMOS design and process. IS93C76A/
86A contains power-efficient read/write memory,
and organization of either 1,024/2,048 bytes of 8
bits or 512/1,024 words of 16 bits. When the
ORG pin is connected to Vcc or left unconnected,
x16 is selected; when it is connected to ground,
x8 is selected.
• Hardware and software write protection
— Defaults to write-disabled state at power-up
— Software instructions for write-enable/disable
• Enhanced low voltage CMOS E2PROM
technology
An instruction set defines the operation of the
devices, including read, write, and mode-enable
functions. To protect against inadvertent data
modification, all erase and write instructions are
accepted only while the device are write-enabled.
• Versatile, easy-to-use Interface
A selected x8 byte or x16 word can be modified
— Self-timed programming cycle
— Automatic erase-before-write
with a single WRITE or ERASE instruction.
Additionally, the two instructions WRITE ALL or DataShee
— Programming status indicator
— Word and chip erasable
DataSheet4U.EcoRmASE ALL can program an entire array. Once a
device begins its self-timed program procedure,
— Chip select enables power savings
the data out pin (Dout) can indicate the READY/
• Durable and reliable
BUSY status by raising chip select (CS). The self-
— 40-year data retention after 1M write cycles
timed write cycle includes an automatic erase-
— 1 million write cycles
before-write capability. The devices can output
— Unlimited read cycles
any number of consecutive bytes/words using a
— Schmitt-trigger Inputs
single READ instruction.
• Industrial and Automotive Temperature Grade
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
DIN
INSTRUCTION
REGISTER
CS
SK
INSTRUCTION
DECODE,
CONTROL,
AND
CLOCK
GENERATION
DATA
REGISTER
ADDRESS
REGISTER
WRITE
ENABLE
DUMMY
BIT
R/W
AMPS
ADDRESS
DECODER
HIGH VOLTAGE
GENERATOR
DOUT
EEPROM
ARRAY
1024/2048x8
512/1024x16
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
DataSheet4Uob.tcaoinmthe latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00F
05/26/05
DataSheet4 U .com
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IS93C86A pdf, ピン配列
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IS93C76A
IS93C86A
ISSI ®
et4U.com
Write Enable (WEN)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done. When Vcc is applied,
this device powers up in the write disabled state. The
device then remains in a write disabled state until a WEN
instruction is executed. Thereafter, the device remains
enabled until a WDS instruction is executed or until Vcc
is removed. (See Figure 4.) (Note: Chip select must
remain LOW until Vcc reaches its operational value.)
Write (WRITE)
The WRITE instruction includes 8 or 16 bits of data to be
written into the specified register. After the last data bit
has been applied to DIN, and before the next rising edge
of SK, CS must be brought LOW. If the device is write-
enabled, then the falling edge of CS initiates the self-
timed programming cycle (see WEN).
Write All (WRALL)
The write all (WRALL) instruction programs all registers with
the data pattern specified in the instruction. As with the
WRITE instruction, the falling edge of CS must occur to
initiate the self-timed programming cycle. If CS is then
brought HIGH after a minimum wait of 200 ns (tCS), the DOUT
pin indicates the READY/BUSY status of the chip (see
Figure 6). Vcc is required to be above 4.5V for WRALL to
function properly.
Write Disable (WDS)
The write disable (WDS) instruction disables all programming
capabilities. This protects the entire device against acci-
dental modification of data until a WEN instruction is
executed. (When Vcc is applied, this part powers up in the
write disabled state.) To protect data, a WDS instruction
should be executed upon completion of each programming
operation.
If CS is brought HIGH, after a minimum wait of 200 ns (5V
Erase Register (ERASE)
operation) after the falling edge of CS (tCS) DOUT will
indicate the READY/BUSY status of the chip. Logical “0”
After the erase instruction is entered, CS must be brought
means programming is still in progress; logical “1” means
LOW. The falling edge of CS initiates the self-timed internal
the selected register has been written, and the part is
ready for another instruction (see Figure 5). The READY/
programming cycle. Bringing CS HIGH after a minimum of
tCS, will cause DOUT to indicate the READ/BUSY status of thDeataShee
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is still in progress;
complete and the
tWP; or b) Simultaneously CS is HIGH, Din is HIGH, and
part is ready for another instruction (see Figure 8).
SK goes HIGH, which clears the status flag.
Erase All (ERAL)
Full chip erase is provided for ease of programming. Erasing
the entire chip involves setting all bits in the entire memory
array to a logical “1” (see Figure 9). Vcc is required to be
above 4.5V for ERALL to function properly.
DataSheet4U.com
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00F
05/26/05
DataSheet4 U .com
3


3Pages


IS93C86A 電子部品, 半導体
www.DataSheet4U.com
IS93C76A
IS93C86A
ISSI ®
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C for Industrial and –40°C to +125°C for Automotive.
Symbol Parameter
Test Conditions
Vcc
Min.
Max.
VOL3
Output LOW Voltage IOL = 100 µA
1.8V to 5.5V
0.2
VOL2
Output LOW Voltage IOL = 100 µA
2.5V to 5.5V
0.2
VOL1
Output LOW Voltage IOL = 2.1mA
4.5V to 5.5V
0.4
VOH3
Output HIGH Voltage IOH = –100 µA
1.8V to 5.5V VCC – 0.2
VOH2
Output HIGH Voltage IOH = –100 µA
2.5V to 5.5V VCC – 0.2
VOH1
Output HIGH Voltage IOH = –400 µA
4.5V to 5.5V
2.4
VIH Input HIGH Voltage
1.8V to 5.5V
2.5V to 5.5V
4.5V to 5.5V
0.7XVCC
0.7XVCC
2.0
VCC+1
VCC+1
VCC+1
VIL Input LOW Voltage
1.8V to 5.5V –0.3 0.2XVCC
2.5V to 5.5V –0.3 0.2XVCC
4.5V to 5.5V
–0.3
0.8
ILI Input Leakage
VIN = 0V to VCC (CS, SK,DIN,ORG)
0 2.5
ILO Output Leakage
VOUT = 0V to VCC, CS = 0V
0
et4U.comN o t e s :
Automotive grade devices in this table are tested with Vcc = 2.5V to 5.5V and 4.5V to 5.5V. Operations with Vcc <2.5V is not specified.
DataSheet4U.com
2.5
Unit
V
V
V
V
V
V
V
V
µA
µA
DataShee
POWER SUPPLY CHARACTERISTICS
TA = –40°C to +85°C for Industrial, and –40°C to +125°C for Automotive.
Symbol
ICC1
ICC2
ISB1
ISB2
Parameter
Test Conditions
Vcc Read Supply Current CS = VIH, SK = 1 MHz, CMOS input levels
CS = VIH, SK = 2 MHz, CMOS input levels
CS = VIH, SK = 2 MHz, CMOS input levels
Vcc Write Supply Current CS = VIH, SK = 1 MHz, CMOS input levels
CS = VIH, SK = 2 MHz, CMOS input levels
CS = VIH, SK = 2 MHz, CMOS input levels
Standby Current
CS = GND, SK = GND,
ORG = Vcc or Floating (x16)
Standby Current
CS = GND, SK = GND,
ORG = GND (x8)
Vcc
1.8V
2.5V
5.0V
1.8V
2.5V
5.0V
1.8V
2.5V
5.0V
1.8V
2.5V
5.0V
Min.
Typ.
0.1
0.2
0.5
0.5
1
2
0.1
0.1
0.2
6
6
10
Max.
1
1
2
1
2
3
1
2
4
10
10
15
Unit
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
DataSheet4U.com
6
DataSheet4 U .com
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00F
05/26/05

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部品番号部品説明メーカ
IS93C86A

(IS93C76A / IS93C86A) 8K-BIT/16K-BIT SERIAL ELECTRICALLY ERASABLE PROM

ISSI
ISSI


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