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UPD29F064115-X の電気的特性と機能

UPD29F064115-XのメーカーはNECです、この部品の機能は「64M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY 4M-WORD BY 16-BIT (WORD MODE) PAGE MODE」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD29F064115-X
部品説明 64M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY 4M-WORD BY 16-BIT (WORD MODE) PAGE MODE
メーカ NEC
ロゴ NEC ロゴ 




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UPD29F064115-X Datasheet, UPD29F064115-X PDF,ピン配置, 機能
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD29F064115-X
64M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY
4M-WORD BY 16-BIT (WORD MODE)
PAGE MODE
Description
The µPD29F064115-X is a flash memory organized of 67,108,864 bits and 142 sectors. Sectors of this memory can
be erased at a low voltage (1.65 to 1.95 V, 1.8 to 2.1 V ) supplied from a power source, or the contents of the entire
chip can be erased. Memory organization is 4,194,304 words × 16 bits, so that the memory can be programmed in
word units. µPD29F064115-X can be read high speed with page mode.
The µPD29F064115-X can be read while its contents are being erased or programmed. The memory cell is divided
into four banks. While sectors in any bank are being erased or programmed, data can be read from the other three
banks thanks to the simultaneous execution architecture. The banks are 8M bits, 24M bits, 24M bits and 8M bits.
Input /output voltage is supplied to 2.7 to 3.3 V.
Because the µPD29F064115-X enables the boot sector to be erased, it is ideal for storing a boot program. In
addition, program code that controls the flash memory can be also stored, and the program code can be programmed
or erased without the need to load it into RAM. 16 small sectors for storing parameters are provided, each of which
can be erased in 4K words units.
Once a program or erase command sequence has been executed, an automatic program or automatic erase
function internally executes program or erase and verification automatically. The programming time is about 0.5
seconds per sector. The erase time is less than 1 second per sector.
Because the µPD29F064115-X can be electrically erased or programmed by writing an instruction, data can be
reprogrammed on-board after the flash memory hDaastabSeehneeints4tUal.lecdomin a system, making it suitable for a wide range of
applications.
This flash memory is packed in 48-pin PLASTIC TSOP (I), 63-pin TAPE FBGA and 85-pin TAPE FBGA.
DataShee
Features
Four bank organization enabling simultaneous execution of program / erase and read
High-speed read with page mode
Bank organization : 4 banks (8M bits + 24M bits + 24M bits + 8M bits)
Memory organization : 4,194,304 words × 16 bits
Sector organization : 142 sectors (4K words × 16 sectors, 32K words × 126 sectors)
The boot sector is located at the highest address (sector) and the lowest address (sector)
3-state output
Automatic program
Program suspend / resume
Unlock bypass program
Automatic erase
Chip erase
Sector erase (sectors can be combined freely)
Erase suspend / resume
Program / Erase completion detection
Detection through data polling and toggle bits
Detection through RY (/BY) pin
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M16062EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
DataSheet4U.com
The mark # shows major revised points.
©
2002
DataSheet4 U .com

1 Page





UPD29F064115-X pdf, ピン配列
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µPD29F064115-X
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP (I) (12 × 20) (Normal bent)
[ µPD29F064115GZ-DB80X-MJH ]
[ µPD29F064115GZ-DB85X-MJH ]
[ µPD29F064115GZ-EB85X-MJH ]
[ µPD29F064115GZ-EB90X-MJH ]
et4U.com
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
/WE
/RESET
A21
/WP (ACC)
RY (/BY)
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Marking Side
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48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0 to A21 : Address inputs
I/O0 to I/O15 : Data Inputs / Outputs
/CE : Chip Enable
/WE : Write Enable
/OE : Output Enable
/RESET
: Hardware reset input
RY (/BY) : Ready (Busy) output
/WP (ACC) : Write Protect (Accelerated) input
VCC : Supply Voltage
VCCQ
: Input / Output Supply Voltage
GND
: Ground
Remark Refer to Package Drawings for the 1-pin index mark.
A16
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
/OE
GND
/CE
A0
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Data Sheet M16062EJ2V0DS
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3Pages


UPD29F064115-X 電子部品, 半導体
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µPD29F064115-X
Block Diagram
VCC
VCCQ
GND
Bank C address
A0 to A21
/WP(ACC)
/RESET
/WE
/CE
/OE
Address
buffers
Bank A address
Bank / Sector
decoder
State
control
(Command
register)
RY(/BY)
Bank B address
Bank D address
X-decoder
Y-decoder
Cell matrix
(Bank A)
Y-gating
Program / Erase
voltage generator
Y-decoder
X-decode
Y-gating
Cell matrix
(Bank B)
X-decoder
Y-decoder
Cell matrix
(Bank C)
Y-gating
SA / WC
Data latch circuit
SA / WC
Y-decoder
Y-gating
X-decoder
Cell matrix
(Bank D)
I/O0 to I/O15
Input / Output
buffers
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Data Sheet M16062EJ2V0DS

6 Page



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部品番号部品説明メーカ
UPD29F064115-X

64M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY 4M-WORD BY 16-BIT (WORD MODE) PAGE MODE

NEC
NEC


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