PDF STA323W Data sheet ( Hoja de datos )

Número de pieza	STA323W
Descripción	2.1 channel high-efficiency digital audio system
Fabricantes	ST Microelectronics
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STA323W 2.1 channel high-efficiency digital audio system PowerSO-36 (slug down) Features  Wide supply voltage range (10 V - 36 V)  Three power output configurations – 2 x 10 W + 1 x 20 W – 2 x 20 W – 1 x 40 W  Thermal protection  Under-voltage protection  Short-circuit protection  PowerSO-36 slug down package  2.1 channels of 24-bit DDX®  100-dB SNR and dynamic range  32 kHz to 192 kHz input sample rates  Digital gain/attenuation +48 dB to -80 dB in 0.5-dB steps  Four 28-bit user programmable biquads (EQ) per channel  I²C control  2-channel I²S input data interface  Individual channel and master gain/attenuation  Individual channel and master soft and hard mute Datasheet - production data  Individual channel volume and EQ bypass  DDX® POP free operation  Bass/treble tone control  Dual independent programmable limiters/compressors  AutoModes™ settings for: – 32 preset EQ curves – 15 preset crossover settings – Auto volume controlled loudness – 3 preset volume curves – 2 preset anti-clipping modes – Preset night-time listening mode – Preset TV AGC  Input and output channel mapping  AM noise-reduction and PWM frequency shifting modes  Soft volume update and muting  Auto zero detect and invalid input detect muting selectable DDX® ternary or binary PWM output plus variable PWM speeds  Selectable de-emphasis  Post-EQ user programmable mix with default 2.1 bass-management settings  Variable max power correction for lower full-power THD  Four output routing configurations  Selectable clock input ratio  96 kHz internal processing sample rate, 24 to 28-bit precision  Video application supports 576 * fs input mode Table 1. Device summary Order code Package STA323W13TR PowerSO-36 in tape & reel February 2014 This is information on a product in full production. DocID11535 Rev 7 1/78 www.st.com 1 page STA323W Contents 8.7 8.8 8.9 8.10 8.6.16 Coefficient b0 data register bits 7:0 (address 0x25) . . . . . . . . . . . . . . . 67 8.6.17 Coefficient write control register (address 0x26) . . . . . . . . . . . . . . . . . . 67 Reading and writing coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.1 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.2 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.3 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.4 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Variable max power correction (address 0x27-0x28) . . . . . . . . . . . . . . . . 70 Fault detect recovery (address 0x2B - 0x2C) . . . . . . . . . . . . . . . . . . . . . . 71 Status indicator register (address 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.10.1 Thermal warning indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.10.2 Fault detect indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.10.3 PLL unlock indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 76 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DocID11535 Rev 7 5/78 78 5 Page STA323W Description 1.1 EQ processing Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block. In these blocks, up to four user-defined Biquads can be applied to each of the two channels. Pre-scaling, DC-blocking high-pass, de-emphasis, bass, and tone control filters can also be implemented by means of configuration parameter settings. The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB bit to 1. The CxEQBP bits can also be used to bypass the EQ functionality on a per channel basis. Figure 3 shows the internal signal flow through the EQ block. Figure 3. Channel signal flow diagram through the EQ block Re-sampled input pre-scale High pass filter BQ#1 BQ#2 BQ#3 BQ#4 De- emphasis Bass filter Treble filter To mix If HPB= 0 4 biquads User defined if AMEQ = 00 Preset EQ if AMEQ = 01 Auto loudness if AMEQ = 10 If CxTCB = 0 If DEMP = 1 BTC: bass boost/cut TTC: treble boost/cut If DSPB = 0 and CxEQB = 0 1.2 Output options Figure 4. Output power stage configurations Half bridge Half bridge Half bridge Half bridge OUT1A OUT1B OUT2A OUT2B Channel 1 2-channel (full bridge) configuration, register bits OCFG[1:0] = 00 Channel 2 Half bridge Half bridge OUT1A OUT1B Half bridge Half bridge OUT2A OUT2B Channel 1 Channel 2 Channel 3 2.1-channel configuration, register bits OCFG[1:0] = 01 Half bridge Half bridge OUT1A OUT1B Half bridge Half bridge OUT2A OUT2B Channel 3 1-channel mono-parallel configuration, register bits OCFG[1:0] = 11 The setup register is Configuration register F (address 0x05) on page 48 DocID11535 Rev 7 11/78 78 11 Page

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