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PDF MX23L6412 Data sheet ( Hoja de datos )
| Número de pieza | MX23L6412 | |
| Descripción | SEQUENTIAL 64M-BIT MASK ROM | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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FEATURES
• Bit organization
- 4M x 16 (word mode only)
- 256 words/page
- Total 16K pages
• Sequential access at 200ns cycle time in a page
• Asynchronous chip enable input (ALEH, ALEL)
• Access time
- Read latency time: 950ns
- Read cycle time: 200ns
- RD access time: 150ns
MX23L6412
SEQUENTIAL 64M-BIT MASK ROM
• Current
- Operating:25mA(max.)
- Address input:2mA(max.)
- Standby:20uA(max.)
• Supply voltage
- 3.0V~3.6V
• Package
- 32 pin TSOP
ORDER INFORMATION
Part No.
Read CycleTime
MX23L6412TC-20
200ns
Package
32 pin TSOP
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GENERAL DESCRIPTION
The product is a 64M bits (4M x 16) mask ROM
composed of 16K pages, and each consists of 256 words
memory cell array. This mask ROM has a 16 bit address
input / data output bus (AD0~AD15), two address latch
enable pins (high : ALEH, low : ALEL), a read strobe
(RD).
There are 3 modes, Stand-by mode, Active mode, and
Address input mode. Stand-by mode is a non-operating
state, and has the smallest current dissipation. Active
mode is an operating state, and data output is possible.
Address input mode is a state of address input.
Address input is through AD bus when ALEL is high.
The high and low 16 bit addresses are latched at
ALEH’sand ALEL falling edges. As for high 16 bit ad-
dress, A0~A6 are through 7 bit address register, A7~A15
are not used internally. As for low 16 bit address, A1~A8
are through 8 bit address counter, A9~A15 are through 7
bit address register, and A0 are not used internally. High
address input must be done before low address input,
and both address inputs are needed for page change or
address change in a same page. After address inputs,
CE goes high at ALEH falling edge and RD doesn't toggle,
the ROM is in stand-by mode.
After ROM turned into Active mode from Address input
mode, it takes tL time to read. In a page, sequential
read access is possible at tCYC cycle time. Sequential
read operation (increment of internal address counter) is
done at every falling edge of RD. At the end of a page,
internal address counter raps around to the beginning of
the page.
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P/N:PM0652
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REV. 1.5, MAR. 11, 2003
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MX23L6412
AC Test Conditions
INPUT
2.4V
0.4V
TEST POINTS
2.4V
0.4V
OUTPUT
2.0V
0.8V
TEST POINTS
2.0V
0.8V
* Input Rise and Fall Times : <10ns
* Output Load : 1TTL+100pF (without active current loading)
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P/N:PM0652
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REV. 1.5, MAR. 11, 2003
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MX23L6412.PDF ] | |
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