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PDF IS64WV12816BLL Data sheet ( Hoja de datos )
| Número de pieza | IS64WV12816BLL | |
| Descripción | (IS61WV12816BLL / IS64WV12816BLL) 128K x 16 HIGH-SPEED CMOS STATIC RAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
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IS61WV12816BLL
IS64WV12816BLL
128K x 16 HIGH-SPEED CMOS STATIC RAM
ISSI®
FEBRUARY 2006
FEATURES
DESCRIPTION
• High-speed access time:
The ISSI IS61WV12816BLL and IS64WV12816BLL are
12 ns: 3.3V + 10%
15 ns: 2.5V-3.6V
high-speed, 2,097,152-bit static RAM organized as 131,072
words by 16 bits. They are fabricated using ISSI's high-
performance CMOS technology. This highly reliable process
• Operating Current: 25mA (typ.)
coupled with innovative circuit design techniques, yields
• Stand by Current: 400µA(typ.)
• TTL and CMOS compatible interface levels
• Fully static operation: no clock or refresh
required
• Three state outputs
access times as fast as 12 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
• Data control for upper and lower bytes
• Industrial and Automotive temperatures avail-
able
• Lead-free available
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
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DataSheet4U.mcoinmi BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128Kx16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
DataSheet4U.comarising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/03/06
DataSheet4 U .com
1
1 page  
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IS61WV12816BLL
IS64WV12816BLL
ISSI ®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol
ICC
Parameter
VDD Operating
Supply Current
Test Conditions
VDD = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
Auto
typ.(2)
-12ns
Min. Max.
— 35
— 40
— 25
-15 ns
Min. Max.
— 30
— 35
— 40
— 20
ISB1 TTL Standby
Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = max
Com.
Ind.
Auto
— 20
— 20
— 20
— 20
— 30
ISB2 CMOS Standby VDD = Max.,
Current
CE ≥ VDD – 0.2V,
(CMOS Inputs)
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Com.
Ind.
Auto
typ.(2)
— 750
— 900
— 400
— 750
— 900
—6
— 400
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=3.3V, TA=250C. Not 100% tested.
Unit
mA
mA
μA
μA
mA
μA
et4U.com CAPACITANCE(1)
Symbol
CIN
Parameter
Input Capacitance
DaCtaoSnhdeiteiot4nUs.com
VIN = 0V
Max.
6
Unit
pF
COUT
Input/Output Capacitance
VOUT = 0V
8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
DataShee
DataSheet4U.com
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/03/06
DataSheet4 U .com
5
5 Page 
www.DataSheet4U.com
IS61WV12816BLL
IS64WV12816BLL
ISSI ®
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
ADDRESS
t WC
ADDRESS 1
t WC
ADDRESS 2
et4U.com
OE
CE LOW
WE
t SA
t HA
t SA
t HA
UB, LB
DOUT
DIN
t PBW
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t PBW
WORD 2
t LZWE
t HD
t SD
DATAIN
VALID
t HD
UB_CEWR4.eps
DataShee
Notes:
DataSheet4U.com
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
DataSheet4U.com
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/03/06
DataSheet4 U .com
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