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PDF HM62V16512L Data sheet ( Hoja de datos )
| Número de pieza | HM62V16512L | |
| Descripción | WIDE TEMPERATURE RANGE VERSION 8 M SRAM | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
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Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
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Pin Arrangement
HM62V16512I Series
48-bumps CSP
1 23456
A LB OE A0 A1 A2 CS2
B I/O8 UB A3 A4 CS1 I/O0
C I/O9 I/O10 A5
A6 I/O1 I/O2
et4U.com
D VSS I/O11 A17 A7 I/O3 VCC
E VCC I/O12 VSS A16 I/O4 VSS
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
H A18 A8
A9 A10 A11 NC
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(Top view)
Pin Description
Pin name
A0 to A18
I/O0 to I/O15
CS1
CS2
WE
OE
LB
UB
VCC
VSS
NC
Function
Address input
Data input/output
Chip select 1
Chip select 2
Write enable
Output enable
Lower byte select
Upper byte select
Power supply
Ground
No connection
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HM62V16512I Series
Write Cycle
HM62V16512I
-5
Parameter
Symbol Min Max Unit Notes
Write cycle time
tWC 55 — ns
Address valid to end of write
tAW 50 — ns
Chip selection to end of write
tCW 50 — ns 5
Write pulse width
tWP 40 — ns 4
LB, UB valid to end of write
tBW 50 — ns
Address setup time
tAS 0 — ns 6
Write recovery time
tWR 0 — ns 7
Data to write time overlap
tDW 25 — ns
Data hold from write time
tDH 0 — ns
Output active from end of write
tOW 5 — ns 2
Output disable to output in High-Z
tOHZ 0 20 ns 1, 2
et4U.coWmrite to output in high-Z
tWHZ 0 20 ns 1, 2
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit
conditions and are not referred to output voltage levels.
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2. This parameter is sampled and noDt a10ta0S%hteeestte4dU..com
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device
and from device to device.
4. A write occures during the overlap of a low CS1, a high CS2, a low WE and a low LB or a low UB.
A write begins at the latest transition among CS1 going low, CS2 going high, WE going low and LB
going low or UB going low. A write ends at the earliest transition among CS1 going high, CS2
going low, WE going high and LB going high or UB going high. tWP is measured from the beginning
of write to the end of write.
5. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
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| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet HM62V16512L.PDF ] | |
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