PDF A80486DX4 Data sheet ( Hoja de datos )

Número de pieza	A80486DX4
Descripción	Embedded Write Back Enhanced
Fabricantes	Intel
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No Preview Available ! www.DataSheet4U.com EMBEDDED WRITE-BACK ENHANCED IntelDX4™ PROCESSOR s Up to 100 MHz Operation s Integrated Floating-Point Unit s Speed-Multiplying Technology s 32-Bit RISC Technology Core s 16-Kbyte Write-Back Cache s 3.3 V Core Operation with 5 V Tolerant I/O Buffers s Burst Bus Cycles s Dynamic Bus Sizing for 8- and 16-bit Data Bus Devices s SL Technology s Data Bus Parity Generation and Checking s Boundary Scan (JTAG) s 3.3-Volt Processor, 75 MHz, 25 MHz CLK — 208-Lead Shrink Quad Flat Pack (SQFP) s 3.3-Volt Processor, 100 MHz, 33 MHz CLK — 208-Lead Shrink Quad Flat Pack (SQFP) — 168-Pin Pin Grid Array (PGA) s Binary Compatible with Large Software Base DataSheet4U.com 64-Bit Interunit Transfer Bus 32-Bit Data Bus 32-Bit Data Bus Barrel Shifter Register File Base/ Index Bus 32 ALU Linear Address 32 DataSheet4U.com PCD PWT Segmentation Unit Descriptor Registers Limit and Attribute PLA Paging Unit 2 Cache Unit 20 Translation Lookaside Buffer Physical Address 16 Kbyte Cache Micro- Instruction Displacement Bus 32 Prefetcher Floating Point Unit Control & Protection Test Unit Instruction Decode Code Stream 24 32-Byte Code Queue 2 x 16 Bytes Floating Point Register File Control ROM Decoded Instruction Path Core Clock Clock Multiplier CLKMUL CLK DataShee Bus Interface 32 Address Drivers A31-A2 BE3#- BE0# Write Buffers 32 4 x 32 D31-D0 Data Bus 32 Transceivers Bus Control Request Sequencer ADS# W/R# D/C# M/IO# PCD PWT RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR NMI SMI# SMIACT# FERR# IGNNE# STPCLK# Burst Bus Control Bus Size Control Cache Control BRDY# BLAST# BS16# BS8# KEN# FLUSH# AHOLD EADS# CACHE# HITM# INV WB/WT# Parity Generation and Control Boundary Scan Control PCHK# DP3-DP0 TCK TMS TDI TDO A3232-01 Figure 1. Embedded Write-Back Enhanced IntelDX4™ Processor Block Diagram © INTEL CORPORATION, 2004 DataSheet4 U .com August 2004 DataSheeOt4rdUe.rcNoummber: 272771-003 1 page www.DataSheet4U.com Embedded Write-Back Enhanced IntelDX4™ Processor 1.0 INTRODUCTION 1.1 Features et4U.com The embedded Write-Back Enhanced IntelDX4™ The Embedded Write-Back Enhanced IntelDX4 processor provides high performance to 32-bit, processor offers these features: embedded applications. Designed for applications that need a floating-point unit, the processor is ideal for embedded designs running DOS, Microsoft Windows, OS/2, or UNIX applications written for the Intel architecture. Projects can be completed quickly using the wide range of software tools, utilities, assemblers and compilers that are available for desktop computer systems. Also, developers can find advantages in using existing chipsets and • 32-bit RISC-Technology Core — The Embedded Write-Back Enhanced IntelDX4 processor performs a complete set of arithmetic and logical operations on 8-, 16-, and 32-bit data types using a full-width ALU and eight general purpose registers. • Single Cycle Execution — Many instructions execute in a single clock cycle. peripheral components in their embedded designs. • Instruction Pipelining — Overlapped instruction fetching, decoding, address translation and The Embedded Write-Back Enhanced IntelDX4 execution. processor is binary compatible with the Intel386™ and earlier Intel processors. Compared with the Intel386 processor, it provides faster execution of many commonly-used instructions. It also provides the benefits of an integrated, 16-Kbyte, write-back cache for code and data. Its data bus can operate in burst mode which provides up to 106-Mbyte-per- second transfers for cache-line fills and instruction prefetches. • On-Chip Floating-Point Unit — Intel486™ processors support the 32-, 64-, and 80-bit formats specified in IEEE standard 754. The unit is binary compatible with the 8087, Intel287™, Intel387™ coprocessors, and Intel OverDrive® processor. • On-Chip Cache with Cache Consistency Support — A 16-Kbyte internal cache is used for both data and instructions. write-back or write-through It is configurable on a line-by-line btoasbiesD. ataShee Intel’s SL Embedded technology is Write-Back EinnchoarnpcoeradtDedaItnaitneSlDhtXehe4et4U.cTporhmoetoincotel,rnwahl iccahcihseapimpplicleambleenttos a modified MESI uniprocessor processor. Utilizing Intel’s System Management systems. Cache hits provide zero wait-state Mode (SMM) enables designers to develop energy- access times for data within the cache. Bus activity efficient systems. is tracked to detect alterations in the memory represented by the internal cache. The internal Two component packages are available: • 168-pin Pin Grid Array (PGA) cache can be invalidated or flushed so that an external cache controller can maintain cache consistency. • 208-lead Shrink Quad Flat Pack (SQFP) • External Cache Control — Write-back and flush The processor operates at either two or three times the external bus frequency. At two times the external bus frequency the processor operates up to 66 MHz, (33-MHz CLK). At three times the external bus frequency the processor operates up to 100 MHz (33-MHz CLK). controls for an external cache are provided so the processor can maintain cache consistency. • On-Chip Memory Management Unit — Address management and memory space protection mechanisms maintain the integrity of memory in a multitasking and virtual memory environment. Both memory segmentation and paging are supported. • Burst Cycles — Burst transfers allow a new double-word to be read from memory on each bus clock cycle. This capability is especially useful for instruction prefetch and for filling the internal cache. Data written from the processor to memory can also be burst transfers. DataSheet4U.com • Write Buffers — The processor contains four write buffers to enhance the performance of consecutive writes to memory. The processor can continue internal operations after a write to these buffers, without waiting for the write to be completed on the external bus. DataSheet4 U .com DataSheet4U.com 1 5 Page www.DataSheet4U.com Embedded Write-Back Enhanced IntelDX4™ Processor et4U.com Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 2 of 2) Pin# Description Pin# Description Pin# Description Pin# Description 36 VSS 88 VSS 140 D4 192 A7 37 M/IO# 89 VCC 141 D3 193 A6 38 VCC 90 DP3 142 D2 194 RESERVED# 39 D/C# 91 D23 143 D1 195 A5 40 PWT 92 D22 144 D0 196 A4 41 PCD 93 D21 145 DP0 197 A3 42 VCC 94 VSS 146 VSS 198 VCC 43 VSS 95 VCC 147 A31 199 VSS 44 VCC 96 NC1 148 A30 200 VCC 45 VCC 97 VSS 149 A29 201 VSS 46 EADS# 98 VCC 150 VCC 202 A2 47 A20M# 99 D20 151 A28 203 ADS# 48 RESET 100 D19 152 A27 204 BLAST# 49 FLUSH# 101 D18 153 A26 205 VCC 50 INTR 102 VCC 154 A25 206 PLOCK# DataShee 51 NMI 103 D17 155 VCC 207 LOCK# 52 VSS 104 DataVSSSheet4U1.c56om VSS 208 VSS NOTE: 1. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors. DataSheet4U.com DataSheet4 U .com DataSheet4U.com 7 11 Page

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