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PDF ISPPAC-POWR604 Data sheet ( Hoja de datos )
| Número de pieza | ISPPAC-POWR604 | |
| Descripción | In-System Programmable Power Supply | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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ispPAC-POWR604
January 2004
In-System Programmable Power Supply
Sequencing Controller and Monitor
Data Sheet
Features
Application Block Diagram
■ Monitor and Control Multiple Power
Supplies
• Simultaneously monitors and sequences up to six
power supplies
• Sequence controller for power-up conditions
• Provides four output control signals
• Programmable digital and analog circuitry
■ Embedded PLD for Sequence Control
• Implements state machine and input conditional
events
• In-System Programmable (ISP™) through JTAG
and on-chip E2CMOS®
■ Embedded Programmable Timers
• Two Programmable 8-bit timers (32µs to 524ms)
• Programmable time delay for pulse stretching or
other power supply management
Voltage Monitor 6
Voltage Monitor 5
2.5-5V Supply
6 Analog Inputs
1.0uF
0.1uF
VMON1
VDD VDDINP
VMON2
VMON3
VMON4
VMON5
VMON6
OUT5
OUT6
OUT7
OUT8
VDD
ispPAC-POWR604
Comp1
Power Sequence Comp2
CLK
Controller
Comp3
Comp4
RESET
Comp5
Comp6
CARD_RESETN
WDT_IN
INT_ACK
DONE
IN1
IN2
IN3
IN4
POR
CREF
CPU_RESETN
BROWNOUT_INT
LOAD_ENABLE
POWER_OK
0.1uF
Digital
Logic
CPU/ASIC
Card etc.
■ Analog Comparators for Monitoring
Description
•
•
Six analog comparators for
192 precise programmable
spanning 1.03V to 5.72V
tmhroensithoorlidngleveDlsataSheetsT4yhUse.tceoLmmatptircoegriasmpPmAaCb®le-PlOogWicRa6n0d4
incorporates both in-
in-system programma-
• Each comparator can be independently config- ble analog circuits to perform special functions for
ured around standard logic supply voltages of
power supply sequencing and monitoring. The ispPAC-
1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V
POWR604 device has the capability to be configured
• Other user-defined voltages possible
through software to control up to four outputs for power
• Six direct comparator outputs
supply sequencing and six comparators monitoring sup-
ply voltage limits, along with four digital inputs for inter-
■ Embedded Oscillator
facing to other control circuits or digital logic. Once
• Built-in clock generator, 250kHz
configured, the design is downloaded into the device
• Programmable clock frequency
through a standard JTAG interface. The circuit configu-
• Programmable timer pre-scaler
ration and routing are stored in non-volatile E2CMOS.
• External clock support
PAC-Designer,® an easy-to-use Windows-compatible
■ Programmable Open-Drain Outputs
• Four digital outputs for logic and power supply
control
• Expandable with ispMACH™ 4000 CPLD
■ 2.25V to 5.5V Supply Range
software package, gives users the ability to design the
logic and sequences that control the power supplies or
regulator circuits. The user has control over timing func-
tions, programmable logic functions and comparator
threshold values as well as I/O configurations.
• In-system programmable at 3.0V to 5.5V
• Industrial temperature range: -40°C to +85°C
• Automotive temperature range: -40°C to +125°C
• 44-pin TQFP package
• Lead-free package option
DataShee
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
DataSheet4Uor.pcroodmuct names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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ispPAC-POWR604 Data Sheet
Recommended Operating Conditions
Symbol
Parameter
Conditions
Min.
Max. Units
VDD
VDDPROG1
VDDINP2
VIN3
VMON
Core supply voltage at pin
Core supply voltage at pin
Digital input supply voltage for IN1-IN4
Input voltage digital inputs
Voltage monitor inputs VMON1 - VMON6
Erase/Program
Cycles
During E2 cell programming
EEPROM, programmed at
VDD = 3.0V to 5.5V
-40°C to +85°C
2.25
3.0
2.25
0
0
1000
5.5 V
5.5 V
5.5 V
5.5 V
6.0 V
— Cycles
TAPROG
Ambient temperature during
programming
-40 +85
°C
TA Ambient temperature
Power applied - Industrial
Power applied - Automotive
-40 +85
-40 +125
°C
°C
1. The ispPAC-POWR604 device must be powered from 3.0V to 5.5V during programming of the E2CMOS memory.
2. VDDINP is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the VDDINP pin with appropriate
supply voltge for the given input logic range.
3. Digital inputs are tolerant up to 5.5V, independent of the VDDINP voltage.
Analog Specifications
Over Recommended Operating Conditions
et4U.com
Symbol
IDD
Reference
Parameter
Supply Current
Conditions
Internal Clock = 250kHz
DataSheet4U.com
Min.
—
Typ.
5
Max.
10
Units
mA
Symbol
Parameter
VREF1
Reference voltage at CREF pin
1. CREF pin requires a 0.1µF capacitor to ground.
Conditions
T = 25°C
Min.
—
Typ.
1.17
Max.
—
Units
V
DataShee
Voltage Monitors
Symbol
RIN
VMON Range
VMON Accuracy
VMON Tempco1
HYST
Parameter
Conditions
Input impedance
Programmable voltage monitor trip
point (192 steps)
Absolute accuracy of any trip point
Temperature drift of any trip point
T = 25 °C,
VDD = 3.3V
-40°C to +85°C
-40°C to +125°C
Hysteresis of VMON input,
VDD = 3.3V, 25°C
VHYST = HYST*VMON (+/-3 to +/-13mV)
PSR
Trip point sensitivity to VDD
1. See typical performance curves.
VDD = 3.3V
Min.
70
1.03
Typ.
100
Max.
130
5.72
Units
kΩ
V
-0.9 +0.9
50
76
+/- 0.3% of
trip point
setting
0.06
%
ppm/ °C
ppm/ °C
%
%/V
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Figure 2. Voltage Monitors
Monitor Voltage
VMON1..VMON6
ispPAC-POWR604 Data Sheet
Reference
To PLD Array
3mV
Hysteresis
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Each monitor consists of three major subsystems. The core of the monitor is a voltage comparator. This compara-
tor outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than that at its negative
terminal, otherwise it outputs a LOW signal. A small amount of hysteresis is provided by the comparator to reduce
the effects of input noise.
The input signal is attenuated by a programmabDlearteasSihsteiveet4dUiv.cidoemr before it is fed into the comparator. This feature
is used to determine the coarse range in which the comparator should trip (e.g. 1.8V, 3.3V, 5V). Twelve possible
ranges are available from the input divider network. The comparator’s negative terminal is obtained from a pro-
grammable reference source (Reference), which may be set to one of 16 possible values scaled in approximately
1% increments from each other, allowing for fine tuning of the voltage monitor’s trip points. This combination of
coarse and fine adjustment supports 192 possible trip-point voltages for a given monitor circuit. Because each
monitor’s reference and input divider settings are completely independent of those of the other monitor circuits, the
user can set any input monitor to any of the 192 available settings.
DataShee
Comparator Hysteresis
VMON
Range Setting1
Typical Hysteresis on Typical Hysteresis on
Over Voltage Range Under Voltage Range
Units
5.0V
+/- 16.2
+/- 14.0
mV
3.3V
+/- 10.7
+/- 9.2
mV
2.5V
+/- 8.1
+/- 7.0
mV
1.8V
+/- 5.8
+/- 5.0
mV
1.5V
+/- 4.9
+/- 4.2
mV
1.2V
+/- 3.9
+/- 3.4
mV
1. The hysteresis scales depending on the voltage monitor range that is selected. The values show are typical and
are centered around the nominal voltage trip point for a given range selection.
PLD Architecture
The ispPAC-POWR604 digital logic is composed of an internal PLD that is programmed to perform the sequencing
functions. The PLD architecture allows flexibility in designing various state machines and control logic used for
monitoring. The macrocell shown in Figure 3 is the heart of the PLD. There are eight macrocells that can be used to
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| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ISPPAC-POWR604.PDF ] | |
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