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ISPPAC20 の電気的特性と機能

ISPPAC20のメーカーはLattice Semiconductorです、この部品の機能は「In-System Programmable Analog Circuit」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISPPAC20
部品説明 In-System Programmable Analog Circuit
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ISPPAC20 Datasheet, ISPPAC20 PDF,ピン配置, 機能
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ispPAC®20
In-System Programmable Analog Circuit
Features
Functional Block Diagram
• IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG
— Two Instrument Amplifier Gain/Attenuation Stages
— Signal Summation (Up to 3 Inputs)
VCC MSEL GND
OUT1
— Precision Active Filtering (10kHz to 100kHz)
— 8-Bit DAC and Fast Dual Comparator
— Non-Volatile E2CMOS® Cells (10,000 Cycles)
— IEEE 1149.1 JTAG Serial Port Programming
• LINEAR ELEMENT BUILDING BLOCKS
IA
IN1
IA OA
— Programmable Gain Range (0dB to 40dB)
— Bandwidth of 550kHz (G=1), 330kHz (G=10)
IN2
— Low Distortion (THD < -74dB max @ 10kHz)
IA
— Auto-Calibrated Input Offset Voltage
• TRUE DIFFERENTIAL I/O
IN3 IA OA
— High CMR (69dB) Instrument Amplifier Inputs
— 2.5V Common Mode Reference on Chip
— Rail-to-Rail Voltage Outputs
— Single Supply 5V Operation
• 44-PIN PLASTIC PLCC AND TQFP PACKAGES
CPIN
Analog Routing Pool
E2CMOS Mem Reference
Auto-Cal
ISP Control
• APPLICATIONS INCLUDE INTEGRATED:
— Single +5V Supply Signal Conditioning
— Active Filters, Gain Stages, Summing Blocks
— Analog Front Ends, 12-Bit Data Acq. Systems
— Precision Voltage Controlled Oscillator
— Synchronous Detection Circuits
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— Precision Rectification & Other Non-Linear Functions
OUT2
CP Logic
CP1OUT
Logic
Window
CP
CP2OUT
3VREF
1.5VREF
DAC
DACOUT
Description
Typical Application Diagram
DataShee
The ispPAC20 is a member of the Lattice family of In-
System Programmable analog circuits, digitally configured
via nonvolatile E2CMOS technology.
Analog building blocks, called PACblocks, replace tradi-
tional analog components such as opamps and active
filters, eliminating the need for most external resistors and
capacitors. Also included are an 8-bit DAC and dual com-
parators. With no requirement for external configuration
components, ispPAC20 expedites the design process,
simplifying prototype circuit implementation and change,
while providing high-performance integrated functionality.
Vin
5V
5V
12-Bit
Differential
Input ADC
Ain+
Ain-
Designers configure the ispPAC20 and verify its perfor-
mance using PAC-Designer®, an easy-to-use, Microsoft
Windows® compatible program. Device programming is
supported using PC parallel port I/O operations.
DAC
Ref+
Ref-
The ispPAC20 is configured through its IEEE Standard
1149.1 (JTAG) compliant serial port. The flexible In-System
Programming capability enables programming, verification
and reconfiguration if desired, directly on the printed circuit
board.
ispPAC20
Copyright © 2001 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
DataSheet4ULA.TcToImCE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
May 2001
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
pac20_05
1
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ISPPAC20 pdf, ピン配列
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Specifications ispPAC20
DC Electrical Characteristics (Continued)
et4U.com
SYMBOL
PARAMETER
Comparator PACells
AV
VOS
VOS/T
PSR
Voltage Gain
Input Offset Voltage
Differential Offset Voltage Drift
Power Supply Rejection
Programmable Hysteresis
tP Propagation Delay
Input Common Mode Input Range
CMRR
Input Common Mode Rejection Ratio
Programming
Erase Program Cycles
Digital I/O
VIL
VIH
IIL, IIH
Input Low Voltage
Input High Voltage
Input Leakage Current
VOL (5)
VOH (5)
Power Supplies
VS
IS
PD
Output Low Voltage
Output High Voltage
Operating Supply Voltage
Supply Current
Power Dissipation
CONDITION
-40 to +85°C
Differential at 1kHz
On or Off
Overdrive = 10mV
Overdrive = 100mV
0V TCK Input VS
0V All Other Inputs VS
IOL = 4.0mA
IOH = -1.0mA
VS = 5.0V
DataSheet4UV.Sco=m5.0V
MIN. TYP. MAX. UNITS
108 dB
5 mV
50 µV/°C
80 dB
±47 mV
750 ns
150 ns
0 5.0 V
60 dB
10K cycles
0 0.8 V
2.0 VS V
±10 µA
+40/-70 µA
0.5 V
2.4 V
4.75
5.0
5.25 V
21 mA
105 mW
DataShee
AC Electrical Characteristics
SYMBOL PARAMETER
CONDITION
MIN. TYP. MAX. UNITS
PACblock Dynamic Performance
THD
Total Harmonic Distortion Differential
Single-Ended
FIN = 10kHz
-88 -74 dB
-72 dB
Differential
Single-Ended
FIN = 100kHz
-67 -62 dB
-63 dB
SNR
Signal to Noise
G = 1 to 10
0.1Hz to 100kHz
103 dB
CMR
BW
Common Mode Rejection (VIN = 1V to 4V)
Note: VIN+ and VIN- connected together
Small Signal Bandwidth G = 1
10kHz
100kHz
69 dB
55 dB
550 kHz
G = 10
330 kHz
BWFP
SR
Full Power Bandwidth
Slew Rate
VIN = 6VDIFF, VOUT = -3dB, G=1
330
5.0 7.5
kHz
V/µs
tS Settling Time
Crosstalk
0.1%
6VDIFF Input Step
Between Any Two Channels
2.0 µs
-90 dB
PACell Filter Characteristics
Filter Pole Programming Range
Number of Poles in Range > 120
10
100 kHz
F0
F0
DF0/DT
Absolute Pole Frequency Accuracy
Pole Step Size (Between Calculated Poles)
Pole Frequency Change vs. Temperature
Deviation From Calculated Value
10kHz to 100kHz
-40 to +85°C
1.0 5.0
%
3.2 %
0.02 %/°C
Notes: (1) A wider input range of 0.7V to 4.3V is typical, but not guaranteed. Inputs larger than this will be clipped. Input signals are also subject
to common-mode voltage limitations. Refer to the table of conditions in this datasheet. (2) Refer to theory of operation section later in this datasheet
for explanation of differential voltage swing computation. (3) To insure full spec performance an additional auto-calibration should be performed
after initial turn-on and the device reaches thermal stability.(4) The user-provided voltage on this pin (CMVIN) becomes an optional (selected via
DataSheet4Upr.ocgorammming) alternative to the default 2.5V VREFOUT. (5) Includes TDO, CP1OUT, CP2OUT and WINDOW output logic pins.
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ISPPAC20 電子部品, 半導体
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Specifications ispPAC20
Timing Specifications (SPI/Parallel Interface Modes)
TA = 25°C; VS = +5.0V (Unless otherwise specified).
SYMBOL
PARAMETER
CONDITION
Dynamic Performance
trenc
Minimum Rising Clock to ENSPI Time
tfenc
Minimum ENSPI to Falling Clock Time
tckmin Minimum Clock Period
tckh TCK High Time
tckl TCK Low Time
tcss CS Setup Time
tcsw
Minimum CS Pulse Widths
tdis TDI Setup Time
tdih TDI Hold Time
tdacs DAC Data Setup Time
tdach DAC Data Hold Time
tdozx TDO Float to Valid Delay
tdov TDO Valid Delay
tdoxz TDO Valid to Float Delay
Timing Specifications (SPI Interface Mode)
et4U.com
trenc tfenc
ENSPI
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tckmin tckh tckl
TCK
tcss
CS
tdis tdih
tcsw
TDI
tdozx
tdov
tdoxz
MIN. TYP. MAX. UNITS
10 ns
10 ns
100 ns
50 ns
50 ns
35 ns
40 ns
15 ns
10 ns
15 ns
10 ns
60 ns
60 ns
60 ns
trenc tfenc
DataShee
TDO
hi-z
hi-z
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共有リンク

Link :


部品番号部品説明メーカ
ISPPAC20

In-System Programmable Analog Circuit

Lattice Semiconductor
Lattice Semiconductor


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