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UT54LVDS032 の電気的特性と機能

UT54LVDS032のメーカーはAeroflex Circuit Technologyです、この部品の機能は「Quad Receiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT54LVDS032
部品説明 Quad Receiver
メーカ Aeroflex Circuit Technology
ロゴ Aeroflex Circuit Technology ロゴ 




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UT54LVDS032 Datasheet, UT54LVDS032 PDF,ピン配置, 機能
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Standard Products
UT54LVDS032 Quad Receiver
Data Sheet
May 22, 2003
FEATURES
INTRODUCTION
q >155.5 Mbps (77.7 MHz) switching rates
q +340mV differential signaling
q 5 V power supply
q TTL compatible outputs
q Ultra low power CMOS technology
q 8.0ns maximum propagation delay
q 3.0ns maximum differential skew
q Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si)and 1Mrad(Si)
- Latchup immune (LET > 111 M eV-cm2/mg)
q Packaging options:
- 16-lead flatpack (dual in-line)
q Standard Microcircuit Drawing 5962-95834
The UT54LVDS032 Quad Receiver is a quad CMOS
differential line receiver designed for applications requiring
ultra low power dissipation and high data rates. The device
is designed to support data rates in excess of 155.5 Mbps
(77.7 MHz) utilizing Low Voltage Differential Signaling
(LVDS) technology.
The UT54LVDS032 accepts low voltage (340mV)
differential input signals and translates them to 5V TTL
output levels. The receiver supports a three-state function
that may be used to multiplex outputs. The receiver also
supports OPEN, shorted and terminated (100 ) input fail-
safe. Receiver output will be HIGH for all fail-safe
conditions.
The UT54LVDS032 and companion quad line driver
UT54LVDS031 provides new alternatives to high power
pseudo-ECL devices for high speed point-to-point interface
applications.
- QML Q and V compliant part
q Compatible with IEEE 1596.3SCI LVDS
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q Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard
DataShee
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RIN1+
RIN1-
+
R1
-
ROUT1
RIN2+
RIN2-
+
R2
-
ROUT2
RIN3+
RIN3-
+
R3
-
ROUT3
RIN4+
RIN4-
EN
EN
+
R4
-
ROUT4
Figure 1. UT54LVDS032 Quad Receiver Block Diagram
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UT54LVDS032 pdf, ピン配列
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Receiver Fail-Safe
The UT54LVDS032 receiver is a high gain, high speed device
that amplifies a small differential signal (20mV) to TTL logic
levels. Due to the high gain and tight threshold of the receiver,
care should be taken to prevent noise from appearing as a valid
signal.
The receiver’s internal fail-safe circuitry is designed to source/
sink a small amount of current, providing fail-safe protection (a
stable known state of HIGH output voltage) for floating,
terminated or shorted receiver inputs.
1. Open Input Pins. The UT54LVDS032 is a quad
receiver device, and if an application requires only 1, 2
or 3 receivers, the unused channel(s) inputs should be
left OPEN. Do not tie unused receiver inputs to ground
or any other voltages. The input is biased by internal high
value pull up and pull down resistors to set the output to
a HIGH state. This internal circuitry will guarantee a
HIGH, stable output state for open inputs.
2. Terminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a three-state condition,
the receiver output will again be in a HIGH state, even
with the end of cable 100termination resistor across
the input pins. The unplugged cable can become a
floating antenna which can pick up noise. If the cable
picks up more than 10mV of differential noise, the
receiver may see the noise as a valid signal and switch.
To insure that any noise is seen as common-mode and
not differential, a balanced interconnect should be used.
Twisted pair cable offers better balance than flat ribbon
cable.
3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output remains in
a HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (VSS to
2.4V). It is only supported with inputs shorted and no
external common-mode voltage applied.
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UT54LVDS032 電子部品, 半導体
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AC SWITCHING CHARACTERISTICS1, 2, 3, 4
(VDD = +5.0V + 10%, TA = -55 °C to +125 °C)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tPHLD
Differential Propagation Delay High to Low
CL = 20pf (figures 4 and 5)
1.0 8.0
ns
tPLHD
Differential Propagation Delay Low to High
CL = 20pf (figures 4 and 5)
1.0 8.0
ns
tSKD
Differential Skew (tPHLD - tPLHD) (figures 4 and 5)
0
3.0
ns
tSK
4
1
tSK
4
2
tTLH4
Channel-to-Channel Skew1 (figures 4 and 5)
Chip-to-Chip Skew5 (figures 4 and 5)
Rise Time (figures 4 and 5)
0 3.0 ns
7.0 ns
2.0 ns
tTHL4
Fall Time (figures 4 and 5)
2.0 ns
tPH
4
Z
Disable Time High to Z (figures 6 and 7)
20 ns
tPLZ 4
Disable Time Low to Z (figures 6 and 7)
20 ns
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tPZ
4
H
tPZL 4
Enable Time Z to High (figures 6 and 7)
Enable Time Z to Low (figures 6 and 7)
20 ns
20 ns DataShee
Notes:
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1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs.
2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z0 = 50 , tr and tf (0% - 100%) < 1ns for R IN and tr and tf < 6ns for EN or EN.
3. CL includes probe and jig capacitance.
4. Guaranteed by characterization.
5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
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部品番号部品説明メーカ
UT54LVDS032

Quad Receiver

Aeroflex Circuit Technology
Aeroflex Circuit Technology


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