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PDF UT54ACS164245S Data sheet ( Hoja de datos )
| Número de pieza | UT54ACS164245S | |
| Descripción | RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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UT54ACS164245S
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver
Datasheet
April , 2002
FEATURES
• Voltage translation
- 5V bus to 3.3V bus
- 3.3V bus to 5V bus
• Cold sparing
- 1MΩ minimum input impedance power-off
LOGIC SYMBOL
O E1 (48)
O E2 (25)
(1)
DIR1
G1
G2 2EN1 (BA)
2EN2 (AB)
1EN1 (BA)
1EN2 (AB)
(47)
1A1
11
(24)
DIR2
(2)
1B1
• 0.6µm Commercial RadHardTM CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
• High speed, low power consumption
• Schmitt trigger inputs to filter noisy signals
• Available QML Q or V processes
• Standard Microcircuit Drawing 5962-98580
• Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640)
(46)
1A2
(44)
1A3
(43)
1A4
(41)
1A5
(40)
1A6
(38)
1A7
(37)
1A8
(36)
2A1
DESCRIPTION
DataSheet4U.co2mA2 (35)
(33)
The 16-bit wide UT54ACS164245S MultiPurpose transceiver
2A3
(32)
is built using UTMC’s Commercial RadHardTM epitaxial
2A4
(30)
2A5
CMOS technology and is ideal for space applications. This high
(29)
2A6
speed, low power UT54ACS164245S transceiver is designed to
(27)
2A7
perform multiple functions including: asynchronous two-way
(26)
2A8
communication, signal buffering, voltage translation, and cold
12
21
22
(3)
1B2
(5)
1B3
(6)
1B4
(8)
1B5
(9)
(11) 1B6
1B7
(12)
1B8
(13)
2B1
(14)
2B2
(16)
2B3
(17)
2B4
(19)
2B5
(20)
2B6
(22)
2B7
(23)
2B8
sparing. With VDD equal to zero volts, the UT54ACS164245S
outputs and inputs present a minimum impedance of 1MΩ mak-
PIN DESCRIPTION
ing it ideal for "cold spare" applications. Balanced outputs and
Pin Names
Description
low "on" output impedance make the UT54ACS164245S well
suited for driving high capacitance loads and low impedance
backplanes. The UT54ACS164245S enables system designers
OE x
DIRx
Output Enable Input (Active Low)
Direction Control Inputs
to interface 3.3 volt CMOS compatible components with 5 volt
xAx Side A Inputs or 3-State Outputs (3.3V Port)
CMOS components. For voltage translation, the A port inter-
faces with the 3.3 volt bus; the B port interfaces with the 5 volt
xBx Side B Inputs or 3-State Outputs (5V Port)
bus. The direction control (DIRx) controls the direction of data FUNCTION TABLE
flow. The output enable (OEx) overrides the direction control
and disables both ports. These signals can be driven from either
port A or B. The direction and output enable controls operate
these devices as either two independent 8-bit transceivers or one
ENABLE
OE x
L
DIRECTION
DIRx
L
OPERATION
B Data To A Bus
16-bit transceiver.
L H A Data To B Bus
HX
Isolation
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DC ELECTRICAL CHARACTERISTICS 1
( -55°C < TC < +125°C) (T C = -55°C to +125°C for "C" screening and -40°C to +125°C for "W" screening)
SYMBOL
PARAMETER
CONDITION
MIN MAX
VT+ Schmitt Trigger, positive going threshold2 VDD from 3.00 to 5.5
.7VDD
VT- Schmitt Trigger, negative going threshold2 VDD from 3.00 to 5.5
.3VDD
VH1 Schmitt Trigger range of hysteresis10
VH2 Schmitt Trigger range of hysteresis10
VDD from 4.5 to 5.5
VDD from 3.00 to 3.6
0.6
0.4
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IIN
IOZ
ICS
IOS1
IOS2
VOL1
VOL2
Input leakage current10
Three-state output leakage current10
Cold sparing leakage current3
Short-circuit output current 6, 11
Short-circuit output current 6, 11
Low-level output voltage4, 10
Low-level output voltage4, 10
VDD from 3.6 to 5.5
VIN = VDD or VSS
VDD from 3.6 to 5.5
VIN = VDD or VSS
VIN = 5.5
VDD = V SS
VO = VDD or VSS
VDD from 4.5 to 5.5
DataVSOhe=eVt4DUD.ocromVSS
VDD from 3.00 to 3.6
IOL= 8mA
IOL= 100µA
VDD = 4.5
IOL= 8mA
IOL= 100µA
VDD = 3.00
-1 3
-1 3
-1 5
-200 200
-100 100
0.4
0.2
0.5
0.2
VOH1 High-level output voltage4, 10
VOH2 High-level output voltage4, 10
IOH= -8mA
IOH= -100µA
VDD = 4.5
IOH= -8mA
IOH= -100µA
VDD = 3.00
VDD - 0.7
VDD - 0.2
VDD - 0.9
VDD - 0.2
UNIT
V
V
V
V
µA
µA
µA
mA
mA
V
V
V
V
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PACKAGE
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1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance with MIL-PRF-38535.
4. Lead position and colanarity are not measured.
5. ID mark symbol is vendor option.
6. With solder, increase maximum by 0.003.
Figure 1. 48-Lead Flatpack
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| PDF Descargar | [ Datasheet UT54ACS164245S.PDF ] | |
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