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ST93C66 の電気的特性と機能

ST93C66のメーカーはST Microelectronicsです、この部品の機能は「(ST93C66 / ST93C67) 4K 256 x 16 or 512 x 8 SERIAL MICROWIRE EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 ST93C66
部品説明 (ST93C66 / ST93C67) 4K 256 x 16 or 512 x 8 SERIAL MICROWIRE EEPROM
メーカ ST Microelectronics
ロゴ ST Microelectronics ロゴ 




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ST93C66 Datasheet, ST93C66 PDF,ピン配置, 機能
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ST93C66
ST93C67
4K (256 x 16 or 512 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
DUAL ORGANIZATION: 256 x 16 or 512 x 8
BYTE/WORD and ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST93C66 version
– 3V to 5.5V for ST93C67 version
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ST93C66 and ST93C67 are replaced by the
M93C66
8
1
PSDIP8 (B)
0.4mm Frame
8
1
SO8 (CM)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
This specification covers a range of 4K bit serial
EEPROM products, the ST93C66 specified at 5V
± 10% and the ST93C67 specified at 3V to 5.5V. In
the text, products are referred to as ST93C66.
The ST93C66 is a 4K bit Electrically Erasable
Programmable Memory (EEPROM) fabricated with
SGS-THOMSON’s High EnduranceSingle Polysili-
con CMOS technology. The memory is accessed
through a serial input (D) and output (Q). The 4K
bit memory is divided into either 512 x 8 bit bytes
or 256 x 16 bit words. The organization may be
selected by a signal applied on the ORG input.
Table 1. Signal Names
S Chip Select Input
D Serial Data Input
Q Serial Data Output
C Serial Clock
ORG
Organisation Select
VCC Supply Voltage
VSS Ground
D
C
S
ORG
VCC
ST93C66
ST93C67
VSS
Q
AI01252B
July 1997
This is information on a product still in production bu t not recommended for new de signs.
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ST93C66 pdf, ピン配列
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ST93C66, ST93C67
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Input Timing Reference Voltages
Output Timing Reference Voltages
20ns
0.4V to 2.4V
1V to 2.0V
0.8V to 2.0V
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Figure 3. AC Testing Input Output Waveforms
2.4V
0.4V
2V
1V
INPUT
OUTPUT
2.0V
0.8V
AI00815
Table 3. Capacitance (1)
(TA = 25 °C, f = 1 MHz )
Symbol
Parameter
CIN Input Capacitance
COUT
Output Capacitance
Note: 1. Sampled only, not 100% tested.
Test Condition
VIN = 0V
VOUT = 0V
Min
Max
Unit
5 pF
5 pF
Table 4. DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V)
Symbol
Parameter
Test Condition
ILI Input Leakage Current
0V VIN VCC
ILO Output Leakage Current
0V VOUT VCC,
Q in Hi-Z
Supply Current (TTL Inputs)
ICC
Supply Current (CMOS Inputs)
ICC1 Supply Current (Standby)
VIL Input Low Voltage (D, C, S)
S = VIH, f = 1 MHz
S = VIH, f = 1 MHz
S = VSS, C = VSS,
ORG = VSS or VCC
VCC = 5V ± 10%
3V VCC 4.5V
VIH Input High Voltage (D, C, S)
VCC = 5V ± 10%
3V VCC 4.5V
VOL Output Low Voltage
VOH Output High Voltage
IOL = 2.1mA
IOL = 10 µA
IOH = –400µA
IOH = –10µA
Min
–0.3
–0.3
2
0.8 VCC
2.4
VCC – 0.2
Max
±2.5
±2.5
3
2
50
0.8
0.2 VCC
VCC + 1
VCC + 1
0.4
0.2
Unit
µA
µA
mA
mA
µA
V
V
V
V
V
V
V
V
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ST93C66 電子部品, 半導体
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ST93C66, ST93C67
INSTRUCTIONS
The ST93C66 has seven instructions, as shown in
Table 6. The op-codes of the instructions are made
up of 2 bits. The op-code is followed by an address
for the byte/word which is eight bits long for the x16
organization or nine bits long for the x8 organiza-
tion. Each instruction is preceded by the rising edge
of the signal applied on the Chip Select (S) input
(assuming that tha Clock C is low). The data input
D is then sampled upon the following rising edges
of the clock C untill a ’1’ is sampled and decoded
by the ST93C66 as a Start bit.
The ST93C66 is fabricated in CMOS technology
and is therefore able to run from zero Hz (static
input signals) up to the maximum ratings (specified
in Table 5).
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de-
coded and the data from the memory is transferred
into an output shift register. A dummy ’0’ bit is output
first, followed by the 8 bit byte or the 16 bit word
with the MSB first. Output data changes are trig-
gered by the Low to High transition of the Clock (C).
The ST93C66 will automatically increment the ad-
dress and will clock out the next byte/word as long
as the Chip Select input (S) is held High. In this
case the dummy ’0’ bit is NOT output between
bytes/words and a continuous stream of data can
be read.
Erase/Write Enable and Disable
The Erase/Write Enable instruction (EWEN)
authorizes the following Erase/Write instructions to
be executed, the Erase/Write Disable instruction
(EWDS) disables the execution of the following
Erase/Write instructions. When power is first ap-
plied, the ST93C66 enters the Disable mode.
When the EWEN instruction is executed, Write
instructions remain enabled until an Erase/Write
Disable instruction (EWDS) is executed or VCC falls
below the power-on reset threshold. To protect the
memory contents from accidental corruption, it is
advisable to issue the EWDS instruction after every
write cycle.
The READ instruction is not affected by the EWEN
or EWDS instructions.
Erase
The Erase instruction (ERASE) programs the ad-
dressed memory byte or word bits to ’1’. Once the
address is correctly decoded, the falling edge of the
Chip Select input (S) triggers a self-timed erase
cycle.
If the ST93C66 is still performing the erase cycle,
the Busy signal (Q = 0) will be returned if S is driven
high, and the ST93C66 will ignore any data on the
bus. When the erase cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the ST93C66 is ready to receive a new instruction.
Write
The Write instruction (WRITE) is followed by the
address and the 8 or 16 data bits to be written. Data
input is sampled on the Low to High transition of
the clock. After the last data bit has been sampled,
Chip Select (S) must be brought Low before the
next rising edge of the clock (C) in order to start
the self-timed programming cycle. If the ST93C66
is still performing the write cycle, the Busy signal
(Q = 0) will be returned if S is driven high, and the
ST93C66 will ignore any data on the bus.
Table 6. Instruction Set
Instruc-
tion
Description
Op-Co de
READ Read Data from Memory
WRITE Write Data to Memory
EWEN Erase/Write Enable
EWDS Erase/Write Disable
ERASE Erase Byte or Word
ERAL Erase All Memory
WRAL
Write All Memory
with same Data
Note: 1. X = don’t care bit.
10
01
00
00
11
00
00
x8 Org
Address
(ORG = 0) (1)
A8-A0
A8-A0
11XXX XXXX
00XXX XXXX
A8-A0
10XXX XXXX
01XXX XXXX
Data
Q7-Q0
D7-D0
D7-D0
x16 Org
Address
(ORG = 1) (1)
A7-A0
A7-A0
11XX XXXX
00XX XXXX
A7-A0
10XX XXXX
01XX XXXX
Data
Q15-Q0
D15-D0
D15-D0
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共有リンク

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部品番号部品説明メーカ
ST93C66

(ST93C66 / ST93C67) 4K 256 x 16 or 512 x 8 SERIAL MICROWIRE EEPROM

ST Microelectronics
ST Microelectronics
ST93C67

(ST93C66 / ST93C67) 4K 256 x 16 or 512 x 8 SERIAL MICROWIRE EEPROM

ST Microelectronics
ST Microelectronics


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