DataSheet.jp

EP1810LC の電気的特性と機能

EP1810LCのメーカーはAlteraです、この部品の機能は「EPLD Family」です。


製品の詳細 ( Datasheet PDF )

部品番号 EP1810LC
部品説明 EPLD Family
メーカ Altera
ロゴ Altera ロゴ 




このページの下部にプレビューとEP1810LCダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

EP1810LC Datasheet, EP1810LC PDF,ピン配置, 機能
www.DataSheet4U.com
May 1999, ver. 5
Features
Classic
® EPLD Family
Data Sheet
s Complete device family with logic densities of 300 to 900 usable gates
(see Table 1)
s Device erasure and reprogramming with non-volatile EPROM
configuration elements
s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies
as high as 100 MHz
s 24 to 68 pins available in dual in-line package (DIP), plastic J-lead
chip carrier (PLCC), pin-grid array (PGA), and small-outline
integrated circuit (SOIC) packages
s Programmable security bit for protection of proprietary designs
s 100% generically tested to provide 100% programming yield
s Programmable registers providing D, T, JK, and SR flipflops with
individual clear and clock controls
s Software design support featuring the Altera® MAX+PLUS® II
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000
workstations, and third-party development systems
s Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems,
and other third-party programming vendors
s Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and VeriBest
Table 1. Classic Device Features
Feature
Usable gates
Macrocells
Maximum user I/O pins
tPD (ns)
fCNT (MHz)
EP610
EP610I
300
16
22
10
100
EP910
EP910I
450
24
38
12
76.9
EP1810
900
48
64
20
50
Altera Corporation
A-DS-CLASSIC-05
DataSheet4 U .com
www.DataSheet4U.com
745
www.DataSheet4U.com

1 Page





EP1810LC pdf, ピン配列
www.DataSheet4U.com
Classic EPLD Family Data Sheet
f
Functional
Description
For more information, see the MAX+PLUS II Programmable Logic
Development System & Software Data Sheet.
The Classic architecture includes the following elements:
s Macrocells
s Programmable registers
s Output enable/clock select
s Feedback select
Macrocells
Classic macrocells, shown in Figure 1, can be individually configured for
both sequential and combinatorial logic operation. Eight product terms
form a programmable-AND array that feeds an OR gate for combinatorial
logic implementation. An additional product term is used for
asynchronous clear control of the internal register; another product term
implements either an output enable or a logic-array-generated clock.
Inputs to the programmable-AND array come from both the true and
complement signals of the dedicated inputs, feedbacks from I/O pins that
are configured as inputs, and feedbacks from macrocell outputs. Signals
from dedicated inputs are globally routed and can feed the inputs of all
device macrocells. The feedback multiplexer controls the routing of
feedback signals from macrocells and from I/O pins. For additional
information on feedback select configurations, see Figure 3 on page 749.
Figure 1. Classic Device Macrocell
Logic Array
Global VCC
Clock
Output Enable/Clock Select
OE
CLK
Input, I/O, and
To Logic Array
Macrocell
Feedbacks Asynchronous Clear
Q
CLR
Programmable
Register
Feedback
Select
Altera Corporation
DataSheet4 U .com
www.DataSheet4U.com
747
www.DataSheet4U.com


3Pages


EP1810LC 電子部品, 半導体
www.DataSheet4U.com
Classic EPLD Family Data Sheet
EP610, EP610I, EP910, and EP910I devices have a global feedback
configuration; either the macrocell output (Q) or the I/O pin input (I/O)
can feed back to the AND array so that it is accessible to all other
macrocells.
EP1810 macrocells can have either of two feedback configurations:
quadrant or dual. Most macrocells in EP1810 devices have a quadrant
feedback configuration; either the macrocell output or I/O pin input can
feed back to other macrocells in the same quadrant. Selected macrocells in
EP1810 devices have a dual feedback configuration: the output of the
macrocell feeds back to other macrocells in the same quadrant, and the
I/O pin input feeds back to all macrocells in the device. If the associated
I/O pin is not used, the macrocell output can optionally feed all
macrocells in the device. In this case, the output of the macrocell passes
through the tri-state buffer and uses the feedback path between the buffer
and the I/O pin.
Design Security
Classic devices contain a programmable security bit that controls access to
the data programmed into the device. When this bit is programmed, a
proprietary design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security because
data within configuration elements is invisible. The security bit that
controls this function and other program data is reset only when the
device is erased.
Timing Model
Device timing can be analyzed with the MAX+PLUS II software, with a
variety of popular industry-standard EDA simulators and timing
analyzers, or with the timing model shown in Figure 4. Devices have fixed
internal delays that allow the user to determine the worst-case timing for
any design. The MAX+PLUS II software provides timing simulation,
point-to-point delay prediction, and detailed timing analysis for system-
level performance evaluation.
Figure 4. Classic Timing Model
Input
Delay
tIN
Global Clock
Delay
tICS
Array Clock
Delay
tIC
I/O
Delay
tIO
Logic Array
Delay
tLAD
tCLR
Register
tSU
tH
Feedback
Delay
tFD
Output
Delay
tOD
tXZ
tZX
750
DataSheet4 U .com
www.DataSheet4U.com
Altera Corporation
www.DataSheet4U.com

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ EP1810LC データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
EP1810LC

EPLD Family

Altera
Altera


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap