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PDF MPC5534 Data sheet ( Hoja de datos )
| Número de pieza | MPC5534 | |
| Descripción | Microcontroller | |
| Fabricantes | Frescale | |
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Freescale Semiconductor
Product Brief
MPC5534PB
Rev. 0.0, 11/2005
MPC5534 Microcontroller
Product Brief
The MPC5534 MCU is the third member of the family of
Table of Contents
next generation microcontrollers based on the
1 Block Diagram ................................................. 4
PowerPCTM Book E architecture. This family of parts
www.DataSheet4U.comcontains many new features coupled with high
2 MPC5500 Family Comparison......................... 5
3 MPC5534 Features List................................... 6
4 MPC5534 Memory Map ................................ 18
performance CMOS technology to provide substantial
5 Detailed Features .......................................... 21
reduction of cost per feature and significant performance
improvement over the MPC500 family.
6 Chip Configuration......................................... 30
7 Documentation .............................................. 31
The host processor core of the MPC5534 is compatible
with the PowerPC Book E architecture. It is 100% user
mode compatible (with floating point library) with the
classic PowerPC instruction set. The Book E architecture
has enhancements that improve the PowerPC
architecture’s fit in embedded applications. This core
also has additional instructions, including digital signal
processing (DSP) instructions, beyond the classic
PowerPC instruction set.
The host processor core of the MPC5534 also includes
an instruction set enhancement allowing variable length
encoding (VLE). This allows optional encoding of mixed
16- and 32-bit instructions. With this enhancement, it is
possible to achieve significant code size footprint
reduction.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
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1 page  
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MPC5500 Family Comparison
2 MPC5500 Family Comparison
Table 1. MPC5500 Family Members
MPC5500 Device
Power PC Core
Variable Length Instruction support
Cache
Memory Management Unit
Crossbar
Core Nexus
SRAM
FLASH
Main Array
Shadow Block
External bus (EBI) Data Bus
Address Bus
MPC5533 MPC5534 MPC5553 MPC5554
e200z3
Yes
None
16 entry
4x5
Class 3+
(NZ3C3)
48k
768K3
1K
16-bit5
24
e200z3
Yes
None
16 entry
4x5
Class 3+
(NZ3C3)
64k
1M3
1K
16 bit5
24
e200z6
No
8k
Unified1
32 entry
4x5
Class 3+
(NZ6C3
64k
1.5M4
1K
32 bit5
24
e200z6
No
32k
Unified2
32 entry
3x5
Class 3+
(NZ6C3)
64k
2M4
1K
32 bit5
24
Calibration Bus
Yes Yes Partial No
Direct Memory Access (DMA)
32 32 32 64
channel channel channel channel
DMA Nexus
None
None Class 3 Class 3
www.DataSheet4U.comSerial
eSCI_A
1222
Yes Yes Yes Yes
eSCI_B
No Yes Yes Yes
Controller Area Network (CAN)
2223
CAN_A
64 buf
64 buf
64 buf
64 buf
CAN_B
No No No 64 buf
CAN_C
64 buf
64 buf
64 buf
64 buf
CAN_D
No No No No
CAN_E
No No No No
SPI 2 3 3 4
DSPI_A
No No No Yes
DSPI_B
No Yes Yes Yes
DSPI_C
Yes Yes Yes Yes
DSPI_D
Yes Yes Yes Yes
eMIOS
0 24 24 24
channel channel channel channel
eTPU
32 32 32 64
channel channel channel channel
eTPU_A
Yes Yes Yes Yes
eTPU_B
No No No Yes
Code memory
12k 12k 12k 16k
Freescale Semiconductor
MPC5534 Microcontroller Product Brief, Rev. 0.0
5
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5 Page 
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MPC5534 Features List
• Selectable drive strengths through pad control in SIU; 10pF, 20pF, 30pF, 50pF
3.8 Calibration Bus
• 21-bit address bus (2 most significant signals multiplexed with 2 chip selects)(Least significant
address bit is not supported - CAL_ADDR31)
• 16-bit data bus
• Memory controller with support for various memory types:
— non-burst SDR Flash and SRAM
— Asynchronous/legacy Flash and SRAM
— Most standard memories used with the MPC5xx family
• Bus monitor (shared with EBI)
— User selectable
— Programmable timeout period (with 8 external bus clock resolution)
• Configurable wait states (via chip selects)
• Three chip-select (CAL_CS[0],CAL_CS[2:3]) signals (CAL_CS[2:3] multiplexed with 2 most
significant address signals CAL_ADDR[10:11])
• Two write/byte enable (WE[0:1]/BE[0:1]) signals
• Configurable bus speed modes (shared with EBI)
— system frequency
www.DataSheet4U.com— 1/2 of system frequency
— 1/4 of system frequency
• Optional automatic CLKOUT gating to save power and reduce EMI
• Compatible with MPC5xx external bus (with some limitations)
• Selectable drive strengths; 10pF, 20pF, 30pF, 50pF
3.9 System Integration Unit (SIU)
• System configuration
— MCU reset configuration via external pins
— Pad configuration control
• System reset monitoring and generation
— Power-on reset support
— Reset status register provides last reset source to software
— Glitch detection on reset input
— Software controlled reset assertion
• External interrupt
Freescale Semiconductor
MPC5534 Microcontroller Product Brief, Rev. 0.0
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MPC5534.PDF ] | |
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