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39SF010 の電気的特性と機能

39SF010のメーカーはSilicon Storage Technologyです、この部品の機能は「(sst39SF010 / SST39SF512) 512 Kbit / 1 Mbit (x8) Multi-Purpose Flash」です。


製品の詳細 ( Datasheet PDF )

部品番号 39SF010
部品説明 (sst39SF010 / SST39SF512) 512 Kbit / 1 Mbit (x8) Multi-Purpose Flash
メーカ Silicon Storage Technology
ロゴ Silicon Storage Technology ロゴ 




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39SF010 Datasheet, 39SF010 PDF,ピン配置, 機能
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512 Kbit / 1 Mbit (x8) Multi-Purpose Flash
SST39SF512 / SST39SF010
FEATURES:
SST39SF512 / 0105.0V 512Kb / 1Mb (x8) MPF memories
Data Sheet
• Organized as 64K x8 / 128K x8
• Single 5.0V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption:
Active Current: 20 mA (typical)
Standby Current: 10 µA (typical)
Sector-Erase Capability
Uniform 4 KByte sectors
Fast Read Access Time:
70 ns
90 ns
Latched Address and Data
Fast Erase and Byte-Program:
Sector-Erase Time: 7 ms (typical)
Chip-Erase Time: 15 ms (typical)
Byte-Program Time: 20 µs (typical)
Chip Rewrite Time:
2 seconds (typical) for SST39SF512
3 seconds (typical) for SST39SF010
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bit
Data# Polling
TTL I/O Compatibility
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
32-pin PLCC
32-pin TSOP (8mm x 14mm)
32-pin PDIP
PRODUCT DESCRIPTION
The SST39SF512/010 are CMOS Multi-Purpose Flash
(MPF) manufactured with SSTs proprietary, high perfor-
mance CMOS SuperFlash technology. The split-gate cell
design and thick oxide tunneling injector attain better reli-
ability and manufacturability compared with alternate
approaches. The SST39SF512/010 devices write (Pro-
gram or Erase) with a 5.0V-only power supply. The
SST39SF512/010 device conforms to JEDEC standard
pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST39SF512/010 devices provide a maximum Byte-Pro-
gram time of 30 µsec. These devices use Toggle Bit or
Data# Polling to indicate the completion of Program opera-
tion. To protect against inadvertent write, they have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST39SF512/010 devices are suited for applications
that require convenient and economical updating of pro-
gram, configuration, or data memory. For all system appli-
cations, they significantly improve performance and
rweliawbwility.,DwahtilaeSlohweereintg4pUo.wceor mconsumption. They inher-
ently use less energy during erase and program than alter-
native flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST39SF512/010 are offered in 32-pin PLCC packages,
32-pin TSOP, and a 600 mil, 32-pin PDIP is also available.
See Figures 1, 2, and 3 for pinouts.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
©2001 Silicon Storage Technology, Inc.
S71149-03-000 4/01
394
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

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39SF010 pdf, ピン配列
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512 Kbit / 1 Mbit Multi-Purpose Flash
SST39SF512 / SST39SF010
Data Sheet
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 0s
and 1s, i.e., toggling between 0 and 1. The Toggle Bit will
begin with 1. When the internal Program or Erase opera-
tion is completed, the toggling will stop. The device is then
ready for the next operation. The Toggle Bit is valid after the
rising edge of fourth WE# (or CE#) pulse for Program oper-
ation. For Sector or Chip-Erase, the Toggle Bit is valid after
the rising edge of sixth WE# (or CE#) pulse. See Figure 8
for Toggle Bit timing diagram and Figure 16 for a flowchart.
Data Protection
The SST39SF512/010 provide both hardware and soft-
ware features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The write operation is
inhibited when VDD is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39SF512/010 provide the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of a series of three byte sequence.
The three byte-load sequence is used to initiate the Pro-
gram operation, providing optimal protection from inadvert-
ent write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six byte load sequence. The SST39SF512 device is
shipped with the Software Data Protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to read mode, within TRC.
Product Identification
The product identification mode identifies the device as the
SST39SF512 and SST39SF010 and manufacturer as
SST. This mode may be accessed by software operations.
Users may use the software product identification operation
to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details, see
Table 3 for hardware operation or Table 4 for software oper-
ation, Figure 11 for the software ID entry and read timing
diagram and Figure 17 for the ID entry command
sequence flowchart.
TABLE 1: PRODUCT IDENTIFICATION
Manufacturers ID
Device ID
SST39LF/VF512
SST39LF/VF010
Address
0000H
0001H
0001H
Data
BFH
B4H
B5H
T1.1 394
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the software reset command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
form and Figure 17 for a flowchart.
www.DataSheet4U.com
©2001 Silicon Storage Technology, Inc.
3
S71149-03-000 4/01 394


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39SF010 電子部品, 半導体
www.DataSheet4U.com
512 Kbit / 1 Mbit Multi-Purpose Flash
SST39SF512 / SST39SF010
Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol
AMS1-A0
Pin Name
Address Inputs
DQ7-DQ0 Data Input/output
CE#
OE#
WE#
VDD
VSS
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Functions
To provide memory addresses.
During Sector-Erase AMS-A12 address lines will select the sector.
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide 5.0V supply (±10%)
Unconnected pins.
1. AMS = Most significant address
AMS = A15 for SST39SF512 and A16 for SST39SF010
T2.3 394
TABLE 3: OPERATION MODES SELECTION
Mode
Read
Program
Erase
CE#
VIL
VIL
VIL
OE#
VIL
VIH
VIH
WE#
VIH
VIL
VIL
DQ
DOUT
DIN
X1
Standby
Write Inhibit
Product Identification
Software Mode
VIH X
X High Z
X VIL X High Z/ DOUT
X X VIH High Z/ DOUT
VIL VIL VIH
1. X can be VIL or VIH, but no other value.
Address
AIN
AIN
Sector address,
XXH for Chip-Erase
X
X
X
See Table 4
T3.4 394
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©2001 Silicon Storage Technology, Inc.
6
S71149-03-000 4/01 394

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共有リンク

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部品番号部品説明メーカ
39SF010

(sst39SF010 / SST39SF512) 512 Kbit / 1 Mbit (x8) Multi-Purpose Flash

Silicon Storage Technology
Silicon Storage Technology
39SF010A

SST39SF010A

SST
SST


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