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PDF SPCP16A Data sheet ( Hoja de datos )
| Número de pieza | SPCP16A | |
| Descripción | Low Speed USB Peripheral Controller | |
| Fabricantes | Sunplus Technology | |
| Logotipo |  |
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SPCP16A
Low-Speed USB Peripheral Controller
t4U.com MAR. 06, 2003
e Version 1.1
SheSUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO.
tais believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.
aContact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by
.DSUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
wwwreasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
1 page  
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SPCP16A
5. FUNCTIONAL DESCRIPTIONS
5.1. Block Diagram
USB Controller
SIE_TX
DP_CK
DM_DA
USB/PS/2
Transceiver
DPLL
SIE_RX
Reset
Circuit
Suspend
Control
suspend
reset
EP1 FIFO
( 8B deep)
data
Registers
Block
data
Control Read
FIFO
(8B deep)
I/O Control
Circuit
Micro-
Controller
5.1.1. Internal USB transceiver architecture
5V VCC
DP_CK
DM_DA
Reset
Circuit
3.3V
Regulator
PORZ
LVRZ
VC
RPPEN
RPUEN
XVR_EN
SUSPND
OEB
5K
5K
1.5K
VDP
VDM
DPI
DMI
+
-
RXD
SUSPD=0: RXD=DP_CK&!DM_DA
SUSPD SUSPD=1: RXD=0
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wwwProprietary & Confidential
5
MAR. 06, 2003
Version: 1.1
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SPCP16A
There is also a mask option, which controls the interrupt trigger
mode. If it is set to "edge trigger mode", the interrupt will then be
triggered by a falling edge on enabled PB pin or by a rising edge
on any of PA0-PA3. Else if the mask option is set to "level trigger
mode", the interrupt is low level triggered by enabled PB pin or
high level triggered by any of PA0-PA3.
3). USB Resume Interrupt
When USB bus enters suspend mode, CPU may be programmed
to enter STOP mode for power savings purpose. At this time, the
only way to wake CPU up is through interrupt. The interrupt can
be triggered by a signal event on the pins such as PB0, PB3, PB4,
PB5, PB6 or PA0-PA3 (must be pre-enabled). After CPU wakes
up, the firmware should upload data to the data FIFO to wake
USB subsystem up; this procedure is called "Remote Wakeup".
The USB subsystem will next generate a "Resume" signal to
indicate USB subsystem has been awakened.
Note: Cares must be exercised while using PA[3:0] and PB pins to trigger
interrupt. Before entering STOP mode, all mask options of enabled
IRQ sources must stay at "inactive state", i.e. PB pins must stay at
high and PA pins must remain at low; otherwise, the interrupt will not
be triggered. For example, suppose PB pins are mask option
selected as IRQ pins and PB4 has been driving low. It causes any
negative edge trigger on other PB pins will not trigger IRQ after
entering STOP mode. That is, program will be stranded in STOP
mode.
4). Timer Interrupt (TIMER)
The timer interrupt is generated by the multi-function timer when
either a timer overflows or a real time interrupt occurs. The Timer
Control & Status Register (TCS, located at $0004) specifies the
timer interrupt flags (TOF, RTIF), enable bits (TOFE and RTIE),
and the timer interrupt acknowledge bits (TOFR and RTIFR). The
i-bit in the processor status flag (inside of CPU) must be cleared to
0 to enable the interrupt.
5.2.1.6. Multi-function timer
The timer for this device is a 15-bit multi-function ripple up-counter.
Functions include Timer Overflow, Real Time Interrupt (RTI),
Power on Reset, and Watchdog Timer reset (WDT). When Timer
Counter Register (TCR $0005) overflows, the Timer Overflow Flag
(TOF) will be set. Moreover, TOF = 1 will result in an interrupt
request to CPU if Timer Overflow Enable is set (TOFE = 1). When
TOFR = 1, the TOF flag bit will be cleared. The Real Time
Interrupt Flag (RTIF) will be set when 1 of 4 selections (RT1, RT0)
is activated. If Real Time Interrupt Enable is set (RTIE = 1) and
when RTIF = 1, an interrupt request will be generated for CPU.
Writing a “1” to RTIFR will clear the RTIF flag bit.
5.2.1.7. Timer registers
The 15-stage timers contain two registers: Timer Counter and
Timer Control/Status Register:
When the USB suspend state is resumed by the USB host, CPU
may still stay in wait mode or stop mode. In this condition, the
“resume” signal can be used to generate an interrupt to notify
firmware that USB has resumed and to exit from wait mode or
stop mode. This procedure is called "Host Resume". The USB
resume interrupt is enabled by IRQE1 ($0006 bit.1), and it is
triggered at the falling edge (functional compatible with PA7
interrupt of SPMC01). When IRQF1 is set ($0006 bit.2 = 1), the
IRQR1 ($0006 bit.7) is used as USB resume interrupt
acknowledge. Writing a "1" to IRQR1 will clear the interrupt flag
IRQF1.
1). Timer Counter Register (TCR) - $0005
The timer counter register is a read-only register, which contains
the present value of the 8-bit timer chain.
2). Timer Control/Status Register (TCS)- $0004
The TCS contains the timer interrupt flag (TOF, RTIF), the timers
interrupt enable (TOFE, RTIE), timers interrupt acknowledge
(TOFR, RTIFR), and the real timers interrupt rate selection bits
(RT1, RT0). Bit 2 and bit 3 are write-only bits and always be read
back as zeros.
TCS1: Timer Control and Status 1 (Addr. 0004h)
mb7 b6 b5
or(0) r(0) r/w(0)
.cTOF
RTIF
TOFE
b4
r/w(0)
RTIE
et4UTOF - Timer Overflow Flag (read-only flag bit.)
eSet to “1” when 8-bit ripple counter rolls over from $FF to
h$00. A timer interrupt request will also be generated if
taSTOFE is set. Writing a “1” to TOFR (TOF acknowledges
abit) will clear TOF to “0”.
.D© Sunplus Technology Co., Ltd.
wwwProprietary & Confidential
b3
w(0)
TOFR
b2
w(0)
RTIFR
b1
r/w(1)
RT1
b0
r/w(1)
RT0
RTIF - Real Time Interrupt Flag (read-only flag bit.)
Set to “1” when output of the chosen Real Time Interrupt
stage goes active. A timer interrupt request will also be
generated if RTIE is also set. Writing a “1” to RTIFR (RTIF
acknowledges bit) will clear RTIF to “0”.
11 MAR. 06, 2003
Version: 1.1
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| PDF Descargar | [ Datasheet SPCP16A.PDF ] | |
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